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chore: account for THUMB BL instruction when mimicking mGBA logs

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-10-21 05:12:04 -03:00
parent 7bc186a03c
commit d714ffb4f9
1 changed files with 8 additions and 1 deletions
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9
src/cpu.zig
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@ -272,7 +272,14 @@ pub const Arm7tdmi = struct {
var log_str: []u8 = undefined;
if (self.cpsr.t.read()) {
log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
if (opcode >> 11 == 0x1E) {
// Instruction 1 of a BL Opcode, print in ARM mode
const tmp_opcode = self.bus.read32(self.r[15] - 2);
const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16;
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
} else {
log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
}
} else {
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
}