chore: rewrite I/O read/writes
This commit is contained in:
parent
601e717850
commit
d4aac22e34
14
src/Bus.zig
14
src/Bus.zig
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@ -63,12 +63,7 @@ pub fn read(self: *const Self, comptime T: type, address: u32) T {
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0x00 => self.bios.read(T, align_addr),
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0x00 => self.bios.read(T, align_addr),
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0x02 => self.ewram.read(T, align_addr),
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0x02 => self.ewram.read(T, align_addr),
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0x03 => self.iwram.read(T, align_addr),
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0x03 => self.iwram.read(T, align_addr),
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0x04 => switch (T) {
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0x04 => io.read(self, T, align_addr),
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u32 => io.read32(self, align_addr),
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u16 => io.read16(self, align_addr),
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u8 => io.read8(self, align_addr),
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else => @compileError("I/O: Unsupported read width"),
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},
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// Internal Display Memory
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// Internal Display Memory
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0x05 => self.ppu.palette.read(T, align_addr),
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0x05 => self.ppu.palette.read(T, align_addr),
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@ -102,12 +97,7 @@ pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
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0x00 => self.bios.write(T, align_addr, value),
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0x00 => self.bios.write(T, align_addr, value),
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0x02 => self.ewram.write(T, align_addr, value),
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0x02 => self.ewram.write(T, align_addr, value),
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0x03 => self.iwram.write(T, align_addr, value),
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0x03 => self.iwram.write(T, align_addr, value),
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0x04 => switch (T) {
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0x04 => io.write(self, T, align_addr, value),
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u32 => io.write32(self, align_addr, value),
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u16 => io.write16(self, align_addr, value),
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u8 => io.write8(self, align_addr, value),
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else => @compileError("I/O: Unsupported write width"),
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},
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// Internal Display Memory
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// Internal Display Memory
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0x05 => self.ppu.palette.write(T, align_addr, value),
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0x05 => self.ppu.palette.write(T, align_addr, value),
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392
src/bus/io.zig
392
src/bus/io.zig
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@ -38,84 +38,32 @@ pub const Io = struct {
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}
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}
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};
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};
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pub fn read32(bus: *const Bus, addr: u32) u32 {
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pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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return switch (addr) {
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return switch (T) {
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u32 => switch (address) {
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// Display
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0004 => @as(u32, bus.ppu.vcount.raw) << 16 | bus.ppu.dispstat.raw,
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0x0400_0004 => @as(T, bus.ppu.vcount.raw) << 16 | bus.ppu.dispstat.raw,
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0x0400_0006 => @as(u32, bus.ppu.bg[0].cnt.raw) << 16 | bus.ppu.vcount.raw,
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0x0400_0006 => @as(T, bus.ppu.bg[0].cnt.raw) << 16 | bus.ppu.vcount.raw,
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// DMA Transfers
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// DMA Transfers
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0x0400_00B8 => @as(u32, bus.dma._0.cnt.raw) << 16,
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0x0400_00B8 => @as(T, bus.dma._0.cnt.raw) << 16,
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0x0400_00C4 => @as(u32, bus.dma._1.cnt.raw) << 16,
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0x0400_00C4 => @as(T, bus.dma._1.cnt.raw) << 16,
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0x0400_00D0 => @as(u32, bus.dma._1.cnt.raw) << 16,
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0x0400_00D0 => @as(T, bus.dma._1.cnt.raw) << 16,
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0x0400_00DC => @as(u32, bus.dma._3.cnt.raw) << 16,
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0x0400_00DC => @as(T, bus.dma._3.cnt.raw) << 16,
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// Timers
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// Timers
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0x0400_0100 => @as(u32, bus.tim._0.cnt.raw) << 16 | bus.tim._0.counter(),
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0x0400_0100 => @as(T, bus.tim._0.cnt.raw) << 16 | bus.tim._0.counter(),
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0x0400_0104 => @as(u32, bus.tim._1.cnt.raw) << 16 | bus.tim._1.counter(),
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0x0400_0104 => @as(T, bus.tim._1.cnt.raw) << 16 | bus.tim._1.counter(),
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0x0400_0108 => @as(u32, bus.tim._2.cnt.raw) << 16 | bus.tim._2.counter(),
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0x0400_0108 => @as(T, bus.tim._2.cnt.raw) << 16 | bus.tim._2.counter(),
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0x0400_010C => @as(u32, bus.tim._3.cnt.raw) << 16 | bus.tim._3.counter(),
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0x0400_010C => @as(T, bus.tim._3.cnt.raw) << 16 | bus.tim._3.counter(),
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// Interrupts
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// Interrupts
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0x0400_0200 => @as(u32, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0200 => @as(T, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0208 => @boolToInt(bus.io.ime),
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0x0400_0208 => @boolToInt(bus.io.ime),
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else => undRead("Tried to read word from 0x{X:0>8}", .{addr}),
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else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
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};
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}
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pub fn write32(bus: *Bus, addr: u32, word: u32) void {
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switch (addr) {
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw = @truncate(u16, word),
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0x0400_0004 => {
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bus.ppu.dispstat.raw = @truncate(u16, word);
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bus.ppu.vcount.raw = @truncate(u16, word >> 16);
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},
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},
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0x0400_0008 => bus.ppu.setAdjCnts(0, word),
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u16 => switch (address) {
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0x0400_000C => bus.ppu.setAdjCnts(2, word),
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0x0400_0010 => bus.ppu.setBgOffsets(0, word),
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0x0400_0014 => bus.ppu.setBgOffsets(1, word),
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0x0400_0018 => bus.ppu.setBgOffsets(2, word),
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0x0400_001C => bus.ppu.setBgOffsets(3, word),
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// Sound
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0x0400_00A0 => log.warn("Wrote 0x{X:0>8} to FIFO_A", .{word}),
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0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{word}),
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// DMA Transfers
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0x0400_00B0 => bus.dma._0.writeSad(word),
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0x0400_00B4 => bus.dma._0.writeDad(word),
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0x0400_00B8 => bus.dma._0.writeCnt(word),
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0x0400_00BC => bus.dma._1.writeSad(word),
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0x0400_00C0 => bus.dma._1.writeDad(word),
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0x0400_00C4 => bus.dma._1.writeCnt(word),
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0x0400_00C8 => bus.dma._2.writeSad(word),
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0x0400_00CC => bus.dma._2.writeDad(word),
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0x0400_00D0 => bus.dma._2.writeCnt(word),
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0x0400_00D4 => bus.dma._3.writeSad(word),
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0x0400_00D8 => bus.dma._3.writeDad(word),
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0x0400_00DC => bus.dma._3.writeCnt(word),
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// Timers
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0x0400_0100 => bus.tim._0.writeCnt(word),
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0x0400_0104 => bus.tim._1.writeCnt(word),
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0x0400_0108 => bus.tim._2.writeCnt(word),
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0x0400_010C => bus.tim._3.writeCnt(word),
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// Serial Communication 1
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0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{word}),
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// Interrupts
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0x0400_0200 => bus.io.setIrqs(word),
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0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{word}),
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0x0400_0208 => bus.io.ime = word & 1 == 1,
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else => undWrite("Tried to write 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }),
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}
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}
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pub fn read16(bus: *const Bus, addr: u32) u16 {
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return switch (addr) {
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// Display
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0000 => bus.ppu.dispcnt.raw,
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0x0400_0004 => bus.ppu.dispstat.raw,
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0x0400_0004 => bus.ppu.dispstat.raw,
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@ -148,100 +96,13 @@ pub fn read16(bus: *const Bus, addr: u32) u16 {
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0x0400_0202 => bus.io.irq.raw,
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0x0400_0202 => bus.io.irq.raw,
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0x0400_0204 => unimplementedRead("Read halfword from WAITCNT", .{}),
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0x0400_0204 => unimplementedRead("Read halfword from WAITCNT", .{}),
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0x0400_0208 => @boolToInt(bus.io.ime),
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0x0400_0208 => @boolToInt(bus.io.ime),
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else => undRead("Tried to read halfword from 0x{X:0>8}", .{addr}),
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else => undRead("Tried to read halfword from 0x{X:0>8}", .{address}),
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};
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},
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}
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u8 => return switch (address) {
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pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
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switch (addr) {
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// Display
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// Display
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0x0400_0000 => bus.ppu.dispcnt.raw = halfword,
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0x0400_0000 => @truncate(T, bus.ppu.dispcnt.raw),
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0x0400_0004 => bus.ppu.dispstat.raw = halfword,
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0x0400_0004 => @truncate(T, bus.ppu.dispstat.raw),
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0x0400_0008 => bus.ppu.bg[0].cnt.raw = halfword,
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0x0400_0006 => @truncate(T, bus.ppu.vcount.raw),
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0x0400_000A => bus.ppu.bg[1].cnt.raw = halfword,
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0x0400_000C => bus.ppu.bg[2].cnt.raw = halfword,
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0x0400_000E => bus.ppu.bg[3].cnt.raw = halfword,
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0x0400_0010 => bus.ppu.bg[0].hofs.raw = halfword, // TODO: Don't write out every HOFS / VOFS?
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0x0400_0012 => bus.ppu.bg[0].vofs.raw = halfword,
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0x0400_0014 => bus.ppu.bg[1].hofs.raw = halfword,
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0x0400_0016 => bus.ppu.bg[1].vofs.raw = halfword,
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0x0400_0018 => bus.ppu.bg[2].hofs.raw = halfword,
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0x0400_001A => bus.ppu.bg[2].vofs.raw = halfword,
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0x0400_001C => bus.ppu.bg[3].hofs.raw = halfword,
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0x0400_001E => bus.ppu.bg[3].vofs.raw = halfword,
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0x0400_0020 => log.warn("Wrote 0x{X:0>4} to BG2PA", .{halfword}),
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0x0400_0026 => log.warn("Wrote 0x{X:0>4} to BG2PD", .{halfword}),
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0x0400_0030 => log.warn("Wrote 0x{X:0>4} to BG3PA", .{halfword}),
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0x0400_0036 => log.warn("Wrote 0x{X:0>4} to BG3PD", .{halfword}),
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0x0400_0040 => log.warn("Wrote 0x{X:0>4} to WIN0H", .{halfword}),
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0x0400_0042 => log.warn("Wrote 0x{X:0>4} to WIN1H", .{halfword}),
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0x0400_0044 => log.warn("Wrote 0x{X:0>4} to WIN0V", .{halfword}),
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0x0400_0046 => log.warn("Wrote 0x{X:0>4} to WIN1V", .{halfword}),
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0x0400_0048 => log.warn("Wrote 0x{X:0>4} to WININ", .{halfword}),
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0x0400_004A => log.warn("Wrote 0x{X:0>4} to WINOUT", .{halfword}),
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0x0400_004C => log.warn("Wrote 0x{X:0>4} to MOSAIC", .{halfword}),
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0x0400_0050 => log.warn("Wrote 0x{X:0>4} to BLDCNT", .{halfword}),
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0x0400_0052 => log.warn("Wrote 0x{X:0>4} to BLDALPHA", .{halfword}),
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0x0400_0054 => log.warn("Wrote 0x{X:0>4} to BLDY", .{halfword}),
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// Sound
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0x0400_0080 => bus.apu.ch_vol_cnt.raw = halfword,
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0x0400_0082 => bus.apu.dma_cnt.raw = halfword,
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0x0400_0084 => bus.apu.setSoundCntX(halfword >> 7 & 1 == 1),
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0x0400_0088 => bus.apu.bias.raw = halfword,
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// Dma Transfers
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0x0400_00B8 => bus.dma._0.writeWordCount(halfword),
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0x0400_00BA => bus.dma._0.writeCntHigh(halfword),
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0x0400_00C4 => bus.dma._1.writeWordCount(halfword),
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0x0400_00C6 => bus.dma._1.writeCntHigh(halfword),
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0x0400_00D0 => bus.dma._2.writeWordCount(halfword),
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0x0400_00D2 => bus.dma._2.writeCntHigh(halfword),
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0x0400_00DC => bus.dma._3.writeWordCount(halfword),
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0x0400_00DE => bus.dma._3.writeCntHigh(halfword),
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// Timers
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0x0400_0100 => bus.tim._0.writeCntLow(halfword),
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0x0400_0102 => bus.tim._0.writeCntHigh(halfword),
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0x0400_0104 => bus.tim._1.writeCntLow(halfword),
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0x0400_0106 => bus.tim._1.writeCntHigh(halfword),
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0x0400_0108 => bus.tim._2.writeCntLow(halfword),
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0x0400_010A => bus.tim._2.writeCntHigh(halfword),
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0x0400_010C => bus.tim._3.writeCntLow(halfword),
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0x0400_010E => bus.tim._3.writeCntHigh(halfword),
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// Serial Communication 1
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0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{halfword}),
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0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{halfword}),
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0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{halfword}),
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0x0400_0126 => log.warn("Wrote 0x{X:0>4} to SIOMULTI3", .{halfword}),
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0x0400_0128 => log.warn("Wrote 0x{X:0>4} to SIOCNT", .{halfword}),
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0x0400_012A => log.warn("Wrote 0x{X:0>4} to SIOMLT_SEND", .{halfword}),
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// Keypad Input
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0x0400_0130 => log.warn("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{halfword}),
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0x0400_0132 => log.warn("Wrote 0x{X:0>4} to KEYCNT", .{halfword}),
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// Serial Communication 2
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0x0400_0134 => log.warn("Wrote 0x{X:0>4} to RCNT", .{halfword}),
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0x0400_0140 => log.warn("Wrote 0x{X:0>4} to JOYCNT", .{halfword}),
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0x0400_0158 => log.warn("Wrote 0x{X:0>4} to JOYSTAT", .{halfword}),
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// Interrupts
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0x0400_0200 => bus.io.ie.raw = halfword,
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0x0400_0202 => bus.io.irq.raw &= ~halfword,
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0x0400_0204 => log.warn("Wrote 0x{X:0>4} to WAITCNT", .{halfword}),
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0x0400_0208 => bus.io.ime = halfword & 1 == 1,
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else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
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}
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}
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pub fn read8(bus: *const Bus, addr: u32) u8 {
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return switch (addr) {
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// Display
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0x0400_0000 => @truncate(u8, bus.ppu.dispcnt.raw),
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0x0400_0004 => @truncate(u8, bus.ppu.dispstat.raw),
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0x0400_0006 => @truncate(u8, bus.ppu.vcount.raw),
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// Sound
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// Sound
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0x0400_0060 => bus.apu.ch1.sweep.raw,
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0x0400_0060 => bus.apu.ch1.sweep.raw,
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@ -250,60 +111,193 @@ pub fn read8(bus: *const Bus, addr: u32) u8 {
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0x0400_0073 => bus.apu.ch3.vol.raw,
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0x0400_0073 => bus.apu.ch3.vol.raw,
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0x0400_0079 => bus.apu.ch4.envelope.raw,
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0x0400_0079 => bus.apu.ch4.envelope.raw,
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0x0400_007C => bus.apu.ch4.poly.raw,
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0x0400_007C => bus.apu.ch4.poly.raw,
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0x0400_0081 => @truncate(u8, bus.apu.ch_vol_cnt.raw >> 8),
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0x0400_0081 => @truncate(T, bus.apu.ch_vol_cnt.raw >> 8),
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0x0400_0089 => @truncate(u8, bus.apu.bias.raw >> 8),
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0x0400_0089 => @truncate(T, bus.apu.bias.raw >> 8),
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// Serial Communication 1
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// Serial Communication 1
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0x0400_0128 => unimplementedRead("Read (low) byte from SIOCNT", .{}),
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0x0400_0128 => unimplementedRead("Read (low) byte from SIOCNT", .{}),
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// Interrupts
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// Interrupts
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0x0400_0200 => @truncate(u8, bus.io.ie.raw),
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0x0400_0200 => @truncate(T, bus.io.ie.raw),
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0x0400_0300 => @enumToInt(bus.io.postflg),
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0x0400_0300 => @enumToInt(bus.io.postflg),
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else => undRead("Tried to read byte from 0x{X:0>8}", .{addr}),
|
else => undRead("Tried to read byte from 0x{X:0>8}", .{address}),
|
||||||
|
},
|
||||||
|
else => @compileError("I/O: Unsupported read width"),
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn write8(bus: *Bus, addr: u32, byte: u8) void {
|
pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
||||||
switch (addr) {
|
return switch (T) {
|
||||||
|
u32 => switch (address) {
|
||||||
// Display
|
// Display
|
||||||
0x0400_0004 => bus.ppu.dispstat.raw = (bus.ppu.dispstat.raw & 0xFF00) | byte,
|
0x0400_0000 => bus.ppu.dispcnt.raw = @truncate(u16, value),
|
||||||
0x0400_0005 => bus.ppu.dispstat.raw = (@as(u16, byte) << 8) | (bus.ppu.dispstat.raw & 0xFF),
|
0x0400_0004 => {
|
||||||
|
bus.ppu.dispstat.raw = @truncate(u16, value);
|
||||||
|
bus.ppu.vcount.raw = @truncate(u16, value >> 16);
|
||||||
|
},
|
||||||
|
0x0400_0008 => bus.ppu.setAdjCnts(0, value),
|
||||||
|
0x0400_000C => bus.ppu.setAdjCnts(2, value),
|
||||||
|
0x0400_0010 => bus.ppu.setBgOffsets(0, value),
|
||||||
|
0x0400_0014 => bus.ppu.setBgOffsets(1, value),
|
||||||
|
0x0400_0018 => bus.ppu.setBgOffsets(2, value),
|
||||||
|
0x0400_001C => bus.ppu.setBgOffsets(3, value),
|
||||||
|
|
||||||
// Sound
|
// Sound
|
||||||
0x0400_0060 => bus.apu.ch1.sweep.raw = byte,
|
0x0400_00A0 => log.warn("Wrote 0x{X:0>8} to FIFO_A", .{value}),
|
||||||
0x0400_0062 => bus.apu.ch1.duty.raw = byte,
|
0x0400_00A4 => log.warn("Wrote 0x{X:0>8} to FIFO_B", .{value}),
|
||||||
0x0400_0063 => bus.apu.ch1.envelope.raw = byte,
|
|
||||||
0x0400_0064 => bus.apu.ch1.setFreqLow(byte),
|
// DMA Transfers
|
||||||
0x0400_0065 => bus.apu.ch1.setFreqHigh(byte),
|
0x0400_00B0 => bus.dma._0.writeSad(value),
|
||||||
0x0400_0068 => bus.apu.ch2.duty.raw = byte,
|
0x0400_00B4 => bus.dma._0.writeDad(value),
|
||||||
0x0400_0069 => bus.apu.ch2.envelope.raw = byte,
|
0x0400_00B8 => bus.dma._0.writeCnt(value),
|
||||||
0x0400_006C => bus.apu.ch2.setFreqLow(byte),
|
0x0400_00BC => bus.dma._1.writeSad(value),
|
||||||
0x0400_006D => bus.apu.ch2.setFreqHigh(byte),
|
0x0400_00C0 => bus.dma._1.writeDad(value),
|
||||||
0x0400_0070 => bus.apu.ch3.select.raw = byte,
|
0x0400_00C4 => bus.dma._1.writeCnt(value),
|
||||||
0x0400_0072 => bus.apu.ch3.length = byte,
|
0x0400_00C8 => bus.dma._2.writeSad(value),
|
||||||
0x0400_0073 => bus.apu.ch3.vol.raw = byte,
|
0x0400_00CC => bus.dma._2.writeDad(value),
|
||||||
0x0400_0074 => bus.apu.ch3.setFreqLow(byte),
|
0x0400_00D0 => bus.dma._2.writeCnt(value),
|
||||||
0x0400_0075 => bus.apu.ch3.setFreqHigh(byte),
|
0x0400_00D4 => bus.dma._3.writeSad(value),
|
||||||
0x0400_0078 => bus.apu.ch4.len = @truncate(u6, byte),
|
0x0400_00D8 => bus.dma._3.writeDad(value),
|
||||||
0x0400_0079 => bus.apu.ch4.envelope.raw = byte,
|
0x0400_00DC => bus.dma._3.writeCnt(value),
|
||||||
0x0400_007C => bus.apu.ch4.poly.raw = byte,
|
|
||||||
0x0400_007D => bus.apu.ch4.cnt.raw = byte,
|
// Timers
|
||||||
0x0400_0080 => bus.apu.setSoundCntLLow(byte),
|
0x0400_0100 => bus.tim._0.writeCnt(value),
|
||||||
0x0400_0081 => bus.apu.setSoundCntLHigh(byte),
|
0x0400_0104 => bus.tim._1.writeCnt(value),
|
||||||
0x0400_0084 => bus.apu.setSoundCntX(byte >> 7 & 1 == 1),
|
0x0400_0108 => bus.tim._2.writeCnt(value),
|
||||||
0x0400_0089 => bus.apu.setBiasHigh(byte),
|
0x0400_010C => bus.tim._3.writeCnt(value),
|
||||||
|
|
||||||
// Serial Communication 1
|
// Serial Communication 1
|
||||||
0x0400_0128 => log.warn("Wrote 0x{X:0>2} to SIOCNT (low)", .{byte}),
|
0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{value}),
|
||||||
|
|
||||||
// Serial Communication 2
|
|
||||||
0x0400_0140 => log.warn("Wrote 0x{X:0>2} to JOYCNT (low)", .{byte}),
|
|
||||||
|
|
||||||
// Interrupts
|
// Interrupts
|
||||||
0x0400_0208 => bus.io.ime = byte & 1 == 1,
|
0x0400_0200 => bus.io.setIrqs(value),
|
||||||
0x0400_0301 => bus.io.haltcnt = if (byte >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
|
0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{value}),
|
||||||
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
|
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||||
}
|
else => undWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }),
|
||||||
|
},
|
||||||
|
u16 => switch (address) {
|
||||||
|
// Display
|
||||||
|
0x0400_0000 => bus.ppu.dispcnt.raw = value,
|
||||||
|
0x0400_0004 => bus.ppu.dispstat.raw = value,
|
||||||
|
0x0400_0008 => bus.ppu.bg[0].cnt.raw = value,
|
||||||
|
0x0400_000A => bus.ppu.bg[1].cnt.raw = value,
|
||||||
|
0x0400_000C => bus.ppu.bg[2].cnt.raw = value,
|
||||||
|
0x0400_000E => bus.ppu.bg[3].cnt.raw = value,
|
||||||
|
0x0400_0010 => bus.ppu.bg[0].hofs.raw = value, // TODO: Don't write out every HOFS / VOFS?
|
||||||
|
0x0400_0012 => bus.ppu.bg[0].vofs.raw = value,
|
||||||
|
0x0400_0014 => bus.ppu.bg[1].hofs.raw = value,
|
||||||
|
0x0400_0016 => bus.ppu.bg[1].vofs.raw = value,
|
||||||
|
0x0400_0018 => bus.ppu.bg[2].hofs.raw = value,
|
||||||
|
0x0400_001A => bus.ppu.bg[2].vofs.raw = value,
|
||||||
|
0x0400_001C => bus.ppu.bg[3].hofs.raw = value,
|
||||||
|
0x0400_001E => bus.ppu.bg[3].vofs.raw = value,
|
||||||
|
0x0400_0020 => log.warn("Wrote 0x{X:0>4} to BG2PA", .{value}),
|
||||||
|
0x0400_0026 => log.warn("Wrote 0x{X:0>4} to BG2PD", .{value}),
|
||||||
|
0x0400_0030 => log.warn("Wrote 0x{X:0>4} to BG3PA", .{value}),
|
||||||
|
0x0400_0036 => log.warn("Wrote 0x{X:0>4} to BG3PD", .{value}),
|
||||||
|
0x0400_0040 => log.warn("Wrote 0x{X:0>4} to WIN0H", .{value}),
|
||||||
|
0x0400_0042 => log.warn("Wrote 0x{X:0>4} to WIN1H", .{value}),
|
||||||
|
0x0400_0044 => log.warn("Wrote 0x{X:0>4} to WIN0V", .{value}),
|
||||||
|
0x0400_0046 => log.warn("Wrote 0x{X:0>4} to WIN1V", .{value}),
|
||||||
|
0x0400_0048 => log.warn("Wrote 0x{X:0>4} to WININ", .{value}),
|
||||||
|
0x0400_004A => log.warn("Wrote 0x{X:0>4} to WINOUT", .{value}),
|
||||||
|
0x0400_004C => log.warn("Wrote 0x{X:0>4} to MOSAIC", .{value}),
|
||||||
|
0x0400_0050 => log.warn("Wrote 0x{X:0>4} to BLDCNT", .{value}),
|
||||||
|
0x0400_0052 => log.warn("Wrote 0x{X:0>4} to BLDALPHA", .{value}),
|
||||||
|
0x0400_0054 => log.warn("Wrote 0x{X:0>4} to BLDY", .{value}),
|
||||||
|
|
||||||
|
// Sound
|
||||||
|
0x0400_0080 => bus.apu.ch_vol_cnt.raw = value,
|
||||||
|
0x0400_0082 => bus.apu.dma_cnt.raw = value,
|
||||||
|
0x0400_0084 => bus.apu.setSoundCntX(value >> 7 & 1 == 1),
|
||||||
|
0x0400_0088 => bus.apu.bias.raw = value,
|
||||||
|
|
||||||
|
// Dma Transfers
|
||||||
|
0x0400_00B8 => bus.dma._0.writeWordCount(value),
|
||||||
|
0x0400_00BA => bus.dma._0.writeCntHigh(value),
|
||||||
|
0x0400_00C4 => bus.dma._1.writeWordCount(value),
|
||||||
|
0x0400_00C6 => bus.dma._1.writeCntHigh(value),
|
||||||
|
0x0400_00D0 => bus.dma._2.writeWordCount(value),
|
||||||
|
0x0400_00D2 => bus.dma._2.writeCntHigh(value),
|
||||||
|
0x0400_00DC => bus.dma._3.writeWordCount(value),
|
||||||
|
0x0400_00DE => bus.dma._3.writeCntHigh(value),
|
||||||
|
|
||||||
|
// Timers
|
||||||
|
0x0400_0100 => bus.tim._0.writeCntLow(value),
|
||||||
|
0x0400_0102 => bus.tim._0.writeCntHigh(value),
|
||||||
|
0x0400_0104 => bus.tim._1.writeCntLow(value),
|
||||||
|
0x0400_0106 => bus.tim._1.writeCntHigh(value),
|
||||||
|
0x0400_0108 => bus.tim._2.writeCntLow(value),
|
||||||
|
0x0400_010A => bus.tim._2.writeCntHigh(value),
|
||||||
|
0x0400_010C => bus.tim._3.writeCntLow(value),
|
||||||
|
0x0400_010E => bus.tim._3.writeCntHigh(value),
|
||||||
|
|
||||||
|
// Serial Communication 1
|
||||||
|
0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{value}),
|
||||||
|
0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{value}),
|
||||||
|
0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{value}),
|
||||||
|
0x0400_0126 => log.warn("Wrote 0x{X:0>4} to SIOMULTI3", .{value}),
|
||||||
|
0x0400_0128 => log.warn("Wrote 0x{X:0>4} to SIOCNT", .{value}),
|
||||||
|
0x0400_012A => log.warn("Wrote 0x{X:0>4} to SIOMLT_SEND", .{value}),
|
||||||
|
|
||||||
|
// Keypad Input
|
||||||
|
0x0400_0130 => log.warn("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{value}),
|
||||||
|
0x0400_0132 => log.warn("Wrote 0x{X:0>4} to KEYCNT", .{value}),
|
||||||
|
|
||||||
|
// Serial Communication 2
|
||||||
|
0x0400_0134 => log.warn("Wrote 0x{X:0>4} to RCNT", .{value}),
|
||||||
|
0x0400_0140 => log.warn("Wrote 0x{X:0>4} to JOYCNT", .{value}),
|
||||||
|
0x0400_0158 => log.warn("Wrote 0x{X:0>4} to JOYSTAT", .{value}),
|
||||||
|
|
||||||
|
// Interrupts
|
||||||
|
0x0400_0200 => bus.io.ie.raw = value,
|
||||||
|
0x0400_0202 => bus.io.irq.raw &= ~value,
|
||||||
|
0x0400_0204 => log.warn("Wrote 0x{X:0>4} to WAITCNT", .{value}),
|
||||||
|
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||||
|
else => undWrite("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ value, address }),
|
||||||
|
},
|
||||||
|
u8 => switch (address) {
|
||||||
|
// Display
|
||||||
|
0x0400_0004 => bus.ppu.dispstat.raw = (bus.ppu.dispstat.raw & 0xFF00) | value,
|
||||||
|
0x0400_0005 => bus.ppu.dispstat.raw = (@as(u16, value) << 8) | (bus.ppu.dispstat.raw & 0xFF),
|
||||||
|
|
||||||
|
// Sound
|
||||||
|
0x0400_0060 => bus.apu.ch1.sweep.raw = value,
|
||||||
|
0x0400_0062 => bus.apu.ch1.duty.raw = value,
|
||||||
|
0x0400_0063 => bus.apu.ch1.envelope.raw = value,
|
||||||
|
0x0400_0064 => bus.apu.ch1.setFreqLow(value),
|
||||||
|
0x0400_0065 => bus.apu.ch1.setFreqHigh(value),
|
||||||
|
0x0400_0068 => bus.apu.ch2.duty.raw = value,
|
||||||
|
0x0400_0069 => bus.apu.ch2.envelope.raw = value,
|
||||||
|
0x0400_006C => bus.apu.ch2.setFreqLow(value),
|
||||||
|
0x0400_006D => bus.apu.ch2.setFreqHigh(value),
|
||||||
|
0x0400_0070 => bus.apu.ch3.select.raw = value,
|
||||||
|
0x0400_0072 => bus.apu.ch3.length = value,
|
||||||
|
0x0400_0073 => bus.apu.ch3.vol.raw = value,
|
||||||
|
0x0400_0074 => bus.apu.ch3.setFreqLow(value),
|
||||||
|
0x0400_0075 => bus.apu.ch3.setFreqHigh(value),
|
||||||
|
0x0400_0078 => bus.apu.ch4.len = @truncate(u6, value),
|
||||||
|
0x0400_0079 => bus.apu.ch4.envelope.raw = value,
|
||||||
|
0x0400_007C => bus.apu.ch4.poly.raw = value,
|
||||||
|
0x0400_007D => bus.apu.ch4.cnt.raw = value,
|
||||||
|
0x0400_0080 => bus.apu.setSoundCntLLow(value),
|
||||||
|
0x0400_0081 => bus.apu.setSoundCntLHigh(value),
|
||||||
|
0x0400_0084 => bus.apu.setSoundCntX(value >> 7 & 1 == 1),
|
||||||
|
0x0400_0089 => bus.apu.setBiasHigh(value),
|
||||||
|
|
||||||
|
// Serial Communication 1
|
||||||
|
0x0400_0128 => log.warn("Wrote 0x{X:0>2} to SIOCNT (low)", .{value}),
|
||||||
|
|
||||||
|
// Serial Communication 2
|
||||||
|
0x0400_0140 => log.warn("Wrote 0x{X:0>2} to JOYCNT (low)", .{value}),
|
||||||
|
|
||||||
|
// Interrupts
|
||||||
|
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||||
|
0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
|
||||||
|
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ value, address }),
|
||||||
|
},
|
||||||
|
else => @compileError("I/O: Unsupported write width"),
|
||||||
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
fn undRead(comptime format: []const u8, args: anytype) u8 {
|
fn undRead(comptime format: []const u8, args: anytype) u8 {
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue