fix: resolve timing regressions

make sure to use fetch timings when fetching instructions
2022-09-28 17:25:21 -03:00
parent 06c60dad74
commit d3514b14f3
2 changed files with 25 additions and 39 deletions
--- a/src/core/cpu/thumb/alu.zig
+++ b/src/core/cpu/thumb/alu.zig
@@ -73,8 +73,6 @@ pub fn fmt4(comptime op: u4) InstrFn {
                    cpu.cpsr.z.write(result == 0);
                    cpu.cpsr.c.write(overflow);
                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
-
-                    // FIXME: Pretty sure CMN Is the same
                },
                0x6 => {
                    // SBC