chore: rename + remove some code

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-06-18 21:36:40 -03:00
parent 4cd722e447
commit c9ea80e03b
3 changed files with 14 additions and 26 deletions

View File

@ -246,33 +246,21 @@ fn DmaController(comptime id: u2) type {
} }
} }
pub fn requestSoundDma(self: *Self, fifo_addr: u32) void { pub fn requestSoundDma(self: *Self, _: u32) void {
comptime std.debug.assert(id == 1 or id == 2); comptime std.debug.assert(id == 1 or id == 2);
if (self.in_progress) { if (self.in_progress) return; // APU must wait their turn
log.err("DMA{} Sound Request but DMA{} is already running?", .{ id, id });
return;
}
if (self.cnt.start_timing.read() != 0b11) { // DMA May not be configured for handling DMAs
log.err("APU requested Sound DMA from DMA{}, but the DMA was not configured for Sound", .{id}); if (self.cnt.start_timing.read() != 0b11) return;
return;
}
// log.err("DMA{}: SAD = 0x{X:0>8}, DAD = 0x{X:0>8}, WC = 0x{X:}", .{ id, self.sad, self.dad, self.word_count });
// log.err("\tSAD Adjustment: {}", .{Self.adjustment(self.cnt.sad_adj.read())});
// log.err("\tDAD Adjustment: {}", .{Self.adjustment(self.cnt.dad_adj.read())});
// log.err("\tRepeat: {}", .{@boolToInt(self.cnt.repeat.read())});
// log.err("\tTransfer Type: {}-bit", .{if (self.cnt.transfer_type.read()) @as(u32, 32) else 16});
// log.err("\tStart Timing: {}", .{self.cnt.start_timing.read()});
// We Assume the Repeat Bit is Set // We Assume the Repeat Bit is Set
// We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr) // We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr)
// We Assume DMACNT_L is set to 4 // We Assume DMACNT_L is set to 4
// FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
// self._dad = fifo_addr;
self.cnt.repeat.set(); self.cnt.repeat.set();
self._dad = fifo_addr;
self._word_count = 4; self._word_count = 4;
self.in_progress = true; self.in_progress = true;
} }

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@ -435,10 +435,10 @@ const InterruptRequest = extern union {
vblank: Bit(u16, 0), vblank: Bit(u16, 0),
hblank: Bit(u16, 1), hblank: Bit(u16, 1),
coincidence: Bit(u16, 2), coincidence: Bit(u16, 2),
tim0_overflow: Bit(u16, 3), tim0: Bit(u16, 3),
tim1_overflow: Bit(u16, 4), tim1: Bit(u16, 4),
tim2_overflow: Bit(u16, 5), tim2: Bit(u16, 5),
tim3_overflow: Bit(u16, 6), tim3: Bit(u16, 6),
serial: Bit(u16, 7), serial: Bit(u16, 7),
dma0: Bit(u16, 8), dma0: Bit(u16, 8),
dma1: Bit(u16, 9), dma1: Bit(u16, 9),

View File

@ -144,10 +144,10 @@ fn Timer(comptime id: u2) type {
if (self.cnt.irq.read()) { if (self.cnt.irq.read()) {
switch (id) { switch (id) {
0 => io.irq.tim0_overflow.set(), 0 => io.irq.tim0.set(),
1 => io.irq.tim1_overflow.set(), 1 => io.irq.tim1.set(),
2 => io.irq.tim2_overflow.set(), 2 => io.irq.tim2.set(),
3 => io.irq.tim3_overflow.set(), 3 => io.irq.tim3.set(),
} }
cpu.handleInterrupt(); cpu.handleInterrupt();