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fix: PC is 12 ahead when it is rd in str and strb

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-02-05 21:42:04 -04:00
parent 7bfb87a859
commit c52dc5adb1
1 changed files with 4 additions and 3 deletions
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7
src/cpu/arm/single_data_transfer.zig
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@ -38,11 +38,12 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
} else {
if (B) {
// STRB
bus.write8(address, @truncate(u8, cpu.r[rd]));
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write8(address, @truncate(u8, value));
} else {
// STR
const force_aligned = address & 0xFFFF_FFFC;
bus.write32(force_aligned, cpu.r[rd]);
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write32(address & 0xFFFF_FFFC, value);
}
}