feat: implement ARM read open bus

src/cpu.zig

@@ -5,7 +5,9 @@ const Bus = @import("Bus.zig");
 const Bit = @import("bitfield").Bit;
 const Bitfield = @import("bitfield").Bitfield;
 const Scheduler = @import("scheduler.zig").Scheduler;
+const FilePaths = @import("util.zig").FilePaths;
 
+const Allocator = std.mem.Allocator;
 const File = std.fs.File;
 
 // ARM Instruction Groups
@@ -59,7 +61,7 @@ pub const Arm7tdmi = struct {
 
     r: [16]u32,
     sched: *Scheduler,
-    bus: *Bus,
+    bus: Bus,
     cpsr: PSR,
     spsr: PSR,
 
@@ -77,11 +79,11 @@ pub const Arm7tdmi = struct {
     log_buf: [0x100]u8,
     binary_log: bool,
 
-    pub fn init(sched: *Scheduler, bus: *Bus) Self {
-        return .{
+    pub fn init(alloc: Allocator, sched: *Scheduler, paths: FilePaths) !Self {
+        var cpu: Arm7tdmi = .{
             .r = [_]u32{0x00} ** 16,
             .sched = sched,
-            .bus = bus,
+            .bus = try Bus.init(alloc, sched, paths),
             .cpsr = .{ .raw = 0x0000_001F },
             .spsr = .{ .raw = 0x0000_0000 },
             .banked_fiq = [_]u32{0x00} ** 10,
@@ -91,6 +93,12 @@ pub const Arm7tdmi = struct {
             .log_buf = undefined,
             .binary_log = false,
         };
+        cpu.bus.cpu = &cpu;
+        return cpu;
+    }
+
+    pub fn deinit(self: Self) void {
+        self.bus.deinit();
     }
 
     pub fn useLogger(self: *Self, file: *const File, is_binary: bool) void {
@@ -250,13 +258,13 @@ pub const Arm7tdmi = struct {
             const opcode = self.thumbFetch();
             if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
 
-            thumb_lut[thumbIdx(opcode)](self, self.bus, opcode);
+            thumb_lut[thumbIdx(opcode)](self, &self.bus, opcode);
         } else {
             const opcode = self.fetch();
             if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
 
             if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
-                arm_lut[armIdx(opcode)](self, self.bus, opcode);
+                arm_lut[armIdx(opcode)](self, &self.bus, opcode);
             }
         }
     }