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feat: upgrade to zig v0.15.1

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note: emu crashes for unknown reason
This commit is contained in:
Rekai Nyangadzayi Musuka
2025-10-12 18:10:12 -05:00
parent 6cacdc7180
commit bd02f625a5
22 changed files with 1083 additions and 5597 deletions
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4
src/core/bus/Bios.zig
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@@ -3,7 +3,7 @@ const std = @import("std");
const Allocator = std.mem.Allocator;
const log = std.log.scoped(.Bios);
const rotr = @import("zba-util").rotr;
const rotr = @import("zba_util").rotr;
const forceAlign = @import("../Bus.zig").forceAlign;
/// Size of the BIOS in bytes
@@ -57,7 +57,7 @@ fn _read(self: *const Self, comptime T: type, addr: u32) T {
}
pub fn write(_: *Self, comptime T: type, addr: u32, value: T) void {
@setCold(true);
@branchHint(.cold);
log.debug("Tried to write {} 0x{X:} to 0x{X:0>8} ", .{ T, value, addr });
}

14
src/core/bus/dma.zig
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@@ -13,7 +13,7 @@ const setHalf = util.setHalf;
const setQuart = util.setQuart;
const handleInterrupt = @import("../cpu_util.zig").handleInterrupt;
const rotr = @import("zba-util").rotr;
const rotr = @import("zba_util").rotr;
pub fn create() DmaTuple {
return .{ DmaController(0).init(), DmaController(1).init(), DmaController(2).init(), DmaController(3).init() };
@@ -286,17 +286,17 @@ fn DmaController(comptime id: u2) type {
if (self._word_count == 0) {
if (self.cnt.irq.read()) {
switch (id) {
0 => bus_ptr.io.irq.dma0.set(),
1 => bus_ptr.io.irq.dma1.set(),
2 => bus_ptr.io.irq.dma2.set(),
3 => bus_ptr.io.irq.dma3.set(),
0 => bus_ptr.io.irq.dma0.write(true),
1 => bus_ptr.io.irq.dma1.write(true),
2 => bus_ptr.io.irq.dma2.write(true),
3 => bus_ptr.io.irq.dma3.write(true),
}
handleInterrupt(cpu);
}
// If we're not repeating, Fire the IRQs and disable the DMA
if (!self.cnt.repeat.read()) self.cnt.enabled.unset();
if (!self.cnt.repeat.read()) self.cnt.enabled.write(false);
// We want to disable our internal enabled flag regardless of repeat
// because we only want to step A DMA that repeats during it's specific
@@ -338,7 +338,7 @@ fn DmaController(comptime id: u2) type {
// FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
// self.dad_latch = fifo_addr;
self.cnt.repeat.set();
self.cnt.repeat.write(true);
self._word_count = 4;
self.in_progress = true;
}

4
src/core/bus/gpio.zig
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@@ -1,5 +1,5 @@
const std = @import("std");
const Bit = @import("bitfield").Bit;
const Bit = @import("bitjuggle").Boolean;
const DateTime = @import("datetime").datetime.Datetime;
const Arm7tdmi = @import("arm32").Arm7tdmi;
@@ -408,7 +408,7 @@ pub const Clock = struct {
// TODO: Confirm that this is the right behaviour
log.debug("Force GamePak IRQ", .{});
bus_ptr.io.irq.game_pak.set();
bus_ptr.io.irq.game_pak.write(true);
handleInterrupt(self.cpu);
}

4
src/core/bus/io.zig
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@@ -5,8 +5,8 @@ const apu = @import("../apu.zig");
const ppu = @import("../ppu.zig");
const util = @import("../../util.zig");
const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield;
const Bit = @import("bitjuggle").Boolean;
const Bitfield = @import("bitjuggle").Bitfield;
const Bus = @import("../Bus.zig");
const getHalf = util.getHalf;

8
src/core/bus/timer.zig
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@@ -200,10 +200,10 @@ fn Timer(comptime id: u2) type {
if (self.cnt.irq.read()) {
switch (id) {
0 => io.irq.tim0.set(),
1 => io.irq.tim1.set(),
2 => io.irq.tim2.set(),
3 => io.irq.tim3.set(),
0 => io.irq.tim0.write(true),
1 => io.irq.tim1.write(true),
2 => io.irq.tim2.write(true),
3 => io.irq.tim3.write(true),
}
handleInterrupt(cpu);