chore: refactor and genericize ARM data processing calculations
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@ -33,186 +33,245 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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// AND
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const result = op1 & op2;
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cpu.r[rd] = result;
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logicFlags(S, cpu, rd, result);
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setArmLogicOpFlags(S, cpu, rd, result);
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},
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0x1 => {
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// EOR
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const result = op1 ^ op2;
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cpu.r[rd] = result;
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logicFlags(S, cpu, rd, result);
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setArmLogicOpFlags(S, cpu, rd, result);
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},
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0x2 => {
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// SUB
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cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
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},
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0x3 => {
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// RSB
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cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
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},
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0x4 => {
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// ADD
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cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
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},
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0x2 => cpu.r[rd] = sub(S, cpu, rd, op1, op2), // SUB
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0x3 => cpu.r[rd] = sub(S, cpu, rd, op2, op1), // RSB
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0x4 => cpu.r[rd] = add(S, cpu, rd, op1, op2), // ADD
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0x5 => {
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// ADC
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var result: u32 = undefined;
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const did = @addWithOverflow(u32, op1, op2, &result);
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const overflow = @addWithOverflow(u32, result, old_carry, &result);
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cpu.r[rd] = result;
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(did or overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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}
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}
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cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
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},
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0x6 => {
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// SBC
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cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
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},
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0x7 => {
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// RSC
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cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
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},
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0x6 => cpu.r[rd] = sbc(S, cpu, rd, op1, op2, old_carry), // SBC
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0x7 => cpu.r[rd] = sbc(S, cpu, rd, op2, op1, old_carry), // RSC
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0x8 => {
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// TST
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if (rd == 0xF) {
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undefinedTestBehaviour(cpu);
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return;
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}
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const result = op1 & op2;
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testFlags(S, cpu, opcode, result);
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setTestOpFlags(S, cpu, opcode, result);
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},
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0x9 => {
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// TEQ
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if (rd == 0xF) {
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undefinedTestBehaviour(cpu);
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return;
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}
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const result = op1 ^ op2;
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testFlags(S, cpu, opcode, result);
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setTestOpFlags(S, cpu, opcode, result);
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},
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0xA => {
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// CMP
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if (rd == 0xF) {
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undefinedTestBehaviour(cpu);
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return;
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}
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const result = op1 -% op2;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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cmp(cpu, op1, op2);
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},
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0xB => {
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// CMN
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if (rd == 0xF) {
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undefinedTestBehaviour(cpu);
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return;
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}
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, op1, op2, &result);
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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cmn(cpu, op1, op2);
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},
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0xC => {
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// ORR
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const result = op1 | op2;
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cpu.r[rd] = result;
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logicFlags(S, cpu, rd, result);
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setArmLogicOpFlags(S, cpu, rd, result);
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},
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0xD => {
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// MOV
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cpu.r[rd] = op2;
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logicFlags(S, cpu, rd, op2);
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setArmLogicOpFlags(S, cpu, rd, op2);
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},
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0xE => {
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// BIC
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const result = op1 & ~op2;
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cpu.r[rd] = result;
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logicFlags(S, cpu, rd, result);
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setArmLogicOpFlags(S, cpu, rd, result);
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},
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0xF => {
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// MVN
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const result = ~op2;
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cpu.r[rd] = result;
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logicFlags(S, cpu, rd, result);
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setArmLogicOpFlags(S, cpu, rd, result);
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},
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}
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}
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}.inner;
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}
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fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = sbc(false, cpu, left, right, old_carry);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = sbc(S, cpu, left, right, old_carry);
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}
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return result;
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}
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pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
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// TODO: Make your own version (thanks peach.bot)
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const subtrahend = @as(u64, right) - old_carry + 1;
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const result = @truncate(u32, left -% subtrahend);
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(subtrahend <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(subtrahend <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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pub fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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fn armSub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = sub(false, cpu, left, right);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = sub(S, cpu, left, right);
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}
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return result;
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}
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pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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const result = left -% right;
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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pub fn add(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = add(false, cpu, left, right);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = add(S, cpu, left, right);
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}
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return result;
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}
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pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, left, right, &result);
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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fn logicFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
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fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = adc(false, cpu, left, right, old_carry);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = adc(S, cpu, left, right, old_carry);
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}
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return result;
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}
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pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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const did = @addWithOverflow(u32, left, right, &result);
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const overflow = @addWithOverflow(u32, result, old_carry, &result);
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(did or overflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
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const result = left -% right;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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pub fn cmn(cpu: *Arm7tdmi, left: u32, right: u32) void {
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, left, right, &result);
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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fn setArmLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
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if (S and rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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setLogicOpFlags(S, cpu, result);
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}
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}
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fn testFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
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fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void {
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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}
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fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TST
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@ -15,7 +15,7 @@ pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
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0b00 => shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset),
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0b01 => shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset),
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0b10 => shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset),
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else => std.debug.panic("{} is an invalid op for Format 1 THUMB Instructions", .{op}),
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else => std.debug.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
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};
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cpu.r[rd] = result;
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@ -16,16 +16,16 @@ pub fn format2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
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if (is_sub) {
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// SUB
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cpu.r[rd] = if (I) blk: {
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break :blk sub(true, cpu, rd, cpu.r[rs], @as(u32, rn));
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break :blk sub(true, cpu, cpu.r[rs], @as(u32, rn));
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} else blk: {
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break :blk sub(true, cpu, rd, cpu.r[rs], cpu.r[rn]);
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break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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} else {
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// ADD
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cpu.r[rd] = if (I) blk: {
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break :blk add(true, cpu, rd, cpu.r[rs], @as(u32, rn));
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break :blk add(true, cpu, cpu.r[rs], @as(u32, rn));
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} else blk: {
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break :blk add(true, cpu, rd, cpu.r[rs], cpu.r[rn]);
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break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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}
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}
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