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feat(cpu): implement MSR and MRS

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-10-21 05:11:55 -03:00
parent e1f8400343
commit b9255bffe7
4 changed files with 47 additions and 8 deletions
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2
src/cpu/barrel_shifter.zig
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@@ -1,7 +1,7 @@
const std = @import("std");
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
const CPSR = @import("../cpu.zig").CPSR;
const CPSR = @import("../cpu.zig").PSR;
pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
var shift_amt: u8 = undefined;

45
src/cpu/psr_transfer.zig
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@@ -4,10 +4,49 @@ const Bus = @import("../Bus.zig");
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
const InstrFn = @import("../cpu.zig").InstrFn;
pub fn psrTransfer(comptime _: bool, comptime _: bool) InstrFn {
pub fn psrTransfer(comptime I: bool, comptime isSpsr: bool) InstrFn {
return struct {
fn inner(_: *Arm7tdmi, _: *Bus, _: u32) void {
std.debug.panic("[CPU] TODO: Implement PSR Transfer Instructions", .{});
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
switch (@truncate(u3, opcode >> 19)) {
0b001 => {
// MRS
const rn = opcode >> 12 & 0xF;
if (isSpsr) {
std.debug.panic("[CPU] TODO: MRS on SPSR_<current_mode> is unimplemented", .{});
} else {
cpu.r[rn] = cpu.cpsr.raw;
}
},
0b101 => {
// MSR
const rm = opcode & 0xF;
switch (@truncate(u3, opcode >> 16)) {
0b000 => {
if (isSpsr) {
std.debug.panic("[CPU] TODO: MSR on SPSR_<current_mode> is unimplemented", .{});
} else {
cpu.cpsr = .{ .raw = cpu.r[rm] };
}
},
0b001 => {
const right = if (I) std.math.rotr(u32, opcode & 0xFF, opcode >> 8 & 0xF) else cpu.r[rm];
if (isSpsr) {
std.debug.panic("[CPU] TODO: MSR (flags only) on SPSR_<current_mode> is unimplemented", .{});
} else {
cpu.cpsr.n.write(right >> 31 & 1 == 1);
cpu.cpsr.z.write(right >> 30 & 1 == 1);
cpu.cpsr.c.write(right >> 29 & 1 == 1);
cpu.cpsr.v.write(right >> 28 & 1 == 1);
}
},
else => unreachable,
}
},
else => unreachable,
}
}
}.inner;
}

2
src/cpu/single_data_transfer.zig
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@@ -4,7 +4,7 @@ const util = @import("../util.zig");
const BarrelShifter = @import("barrel_shifter.zig");
const Bus = @import("../Bus.zig");
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
const CPSR = @import("../cpu.zig").CPSR;
const CPSR = @import("../cpu.zig").PSR;
const InstrFn = @import("../cpu.zig").InstrFn;
pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {