feat: implement ui for register, interrupt

2023-01-07 01:24:51 -06:00
parent fe6fc0e517
commit ae78588b80
3 changed files with 126 additions and 20 deletions
--- a/src/core/bus/io.zig
+++ b/src/core/bus/io.zig
@@ -346,10 +346,10 @@ const InterruptEnable = extern union {
    vblank: Bit(u16, 0),
    hblank: Bit(u16, 1),
    coincidence: Bit(u16, 2),
-    tm0_overflow: Bit(u16, 3),
-    tm1_overflow: Bit(u16, 4),
-    tm2_overflow: Bit(u16, 5),
-    tm3_overflow: Bit(u16, 6),
+    tim0: Bit(u16, 3),
+    tim1: Bit(u16, 4),
+    tim2: Bit(u16, 5),
+    tim3: Bit(u16, 6),
    serial: Bit(u16, 7),
    dma0: Bit(u16, 8),
    dma1: Bit(u16, 9),