chore: don't panic on 32-bit I/O

src/Bus.zig

@@ -57,9 +57,9 @@ pub fn read32(self: *const Self, addr: u32) u32 {
         0x0A00_0000...0x0BFF_FFFF => self.pak.get32(addr - 0x0A00_0000),
         0x0C00_0000...0x0DFF_FFFF => self.pak.get32(addr - 0x0C00_0000),
 
-        else => {
+        else => blk: {
             log.warn("32-bit read from 0x{X:0>8}", .{addr});
-            return 0x0000_0000;
+            break :blk 0x0000_0000;
         },
     };
 }
@@ -100,10 +100,7 @@ pub fn read16(self: *const Self, addr: u32) u16 {
         0x0A00_0000...0x0BFF_FFFF => self.pak.get16(addr - 0x0A00_0000),
         0x0C00_0000...0x0DFF_FFFF => self.pak.get16(addr - 0x0C00_0000),
 
-        else => {
+        else => std.debug.panic("16-bit read from 0x{X:0>8}", .{addr}),
-            log.warn("16-bit read from 0x{X:0>8}", .{addr});
-            return 0x0000;
-        },
     };
 }
 
@@ -120,7 +117,7 @@ pub fn write16(self: *Self, addr: u32, halfword: u16) void {
         0x0600_0000...0x0601_7FFF => self.ppu.vram.set16(addr - 0x0600_0000, halfword),
         0x0700_0000...0x0700_03FF => self.ppu.oam.set16(addr - 0x0700_0000, halfword),
 
-        else => log.warn("16-bit write of 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
+        else => std.debug.panic("16-bit write of 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }),
     }
 }
 
@@ -143,10 +140,7 @@ pub fn read8(self: *const Self, addr: u32) u8 {
         0x0C00_0000...0x0DFF_FFFF => self.pak.get8(addr - 0x0C00_0000),
         0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] read from 0x{X:} in Game Pak SRAM", .{addr}),
 
-        else => {
+        else => std.debug.panic("8-bit read from 0x{X:0>8}", .{addr}),
-            log.warn("8-bit read from 0x{X:0>8}", .{addr});
-            return 0x00;
-        },
     };
 }
 
@@ -159,6 +153,6 @@ pub fn write8(self: *Self, addr: u32, byte: u8) void {
 
         // External Memory (Game Pak)
         0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] write 0x{X:} to 0x{X:} in Game Pak SRAM", .{ byte, addr }),
-        else => log.warn("8-bit write of 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
+        else => std.debug.panic("8-bit write of 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }),
     }
 }

src/bus/Bios.zig

@@ -30,19 +30,19 @@ pub fn get32(self: *const Self, idx: usize) u32 {
     if (self.buf) |buf|
         return (@as(u32, buf[idx + 3]) << 24) | (@as(u32, buf[idx + 2]) << 16) | (@as(u32, buf[idx + 1]) << 8) | (@as(u32, buf[idx]));
 
-    std.debug.panic("[CPU|BIOS:32] ZBA tried to read from 0x{X:0>8} but no BIOS was provided.", .{idx});
+    std.debug.panic("[CPU/BIOS:32] ZBA tried to read from 0x{X:0>8} but no BIOS was provided.", .{idx});
 }
 
 pub fn get16(self: *const Self, idx: usize) u16 {
     if (self.buf) |buf|
         return (@as(u16, buf[idx + 1]) << 8) | @as(u16, buf[idx]);
 
-    std.debug.panic("[CPU|BIOS:16] ZBA tried to read from 0x{X:0>8} but no BIOS was provided.", .{idx});
+    std.debug.panic("[CPU/BIOS:16] ZBA tried to read from 0x{X:0>8} but no BIOS was provided.", .{idx});
 }
 
 pub fn get8(self: *const Self, idx: usize) u8 {
     if (self.buf) |buf|
         return buf[idx];
 
-    std.debug.panic("[CPU|BIOS:8] ZBA tried to read from 0x{X:0>8} but no BIOS was provided.", .{idx});
+    std.debug.panic("[CPU/BIOS:8] ZBA tried to read from 0x{X:0>8} but no BIOS was provided.", .{idx});
 }

src/bus/io.zig

@@ -137,7 +137,7 @@ pub fn read32(bus: *const Bus, addr: u32) u32 {
         0x0400_0006 => bus.ppu.vcount.raw,
         0x0400_0200 => bus.io.ie.raw,
         0x0400_0208 => @boolToInt(bus.io.ime),
-        else => std.debug.panic("[I/O:32] tried to read from {X:}", .{addr}),
+        else => std.debug.panic("[Io:32] tried to read from {X:}", .{addr}),
     };
 }
 
@@ -162,7 +162,7 @@ pub fn write32(bus: *Bus, addr: u32, word: u32) void {
         },
         0x0400_0200 => bus.io.ie.raw = @truncate(u16, word),
         0x0400_0208 => bus.io.ime = word & 1 == 1,
-        else => std.debug.panic("[I/O:32] tried to write 0x{X:} to 0x{X:}", .{ word, addr }),
+        else => std.debug.panic("[Io:32] tried to write 0x{X:} to 0x{X:}", .{ word, addr }),
     }
 }
 
@@ -174,7 +174,7 @@ pub fn read16(bus: *const Bus, addr: u32) u16 {
         0x0400_0130 => bus.io.keyinput.raw,
         0x0400_0200 => bus.io.ie.raw,
         0x0400_0208 => @boolToInt(bus.io.ime),
-        else => std.debug.panic("[I/O:16] tried to read from {X:}", .{addr}),
+        else => std.debug.panic("[Io:16] tried to read from {X:}", .{addr}),
     };
 }
 
@@ -194,7 +194,7 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void {
         0x0400_0200 => bus.io.ie.raw = halfword,
         0x0400_0202 => bus.io.irq.raw = halfword,
         0x0400_0208 => bus.io.ime = halfword & 1 == 1,
-        else => std.debug.panic("[I/O:16] tried to write 0x{X:} to 0x{X:}", .{ halfword, addr }),
+        else => std.debug.panic("[Io:16] tried to write 0x{X:} to 0x{X:}", .{ halfword, addr }),
     }
 }
 
@@ -204,7 +204,7 @@ pub fn read8(bus: *const Bus, addr: u32) u8 {
         0x0400_0004 => @truncate(u8, bus.ppu.dispstat.raw),
         0x0400_0200 => @truncate(u8, bus.io.ie.raw),
         0x0400_0006 => @truncate(u8, bus.ppu.vcount.raw),
-        else => std.debug.panic("[I/O:8] tried to read from {X:}", .{addr}),
+        else => std.debug.panic("[Io:8] tried to read from {X:}", .{addr}),
     };
 }
 
@@ -212,6 +212,6 @@ pub fn write8(self: *Bus, addr: u32, byte: u8) void {
     switch (addr) {
         0x0400_0208 => self.io.ime = byte & 1 == 1,
         0x0400_0301 => self.io.is_halted = byte >> 7 & 1 == 0, // TODO: Implement Stop?
-        else => std.debug.panic("[I/0:8] tried to write 0x{X:} to 0x{X:}", .{ byte, addr }),
+        else => std.debug.panic("[Io:8] tried to write 0x{X:} to 0x{X:}", .{ byte, addr }),
     }
 }

src/cpu.zig

@@ -118,7 +118,7 @@ pub const Arm7tdmi = struct {
             .Undefined => 2,
             .Irq => 3,
             .Fiq => 4,
-            else => std.debug.panic("{} does not have a SPSR Register", .{mode}),
+            else => std.debug.panic("[CPU/Mode] {} does not have a SPSR Register", .{mode}),
         };
     }
 
@@ -442,7 +442,7 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
         0xC => !cpsr.z.read() and (cpsr.n.read() == cpsr.v.read()), // GT - Greater than
         0xD => cpsr.z.read() or (cpsr.n.read() != cpsr.v.read()), // LE - Less than or equal
         0xE => true, // AL - Always
-        0xF => std.debug.panic("[CPU] 0xF is a reserved condition field", .{}),
+        0xF => std.debug.panic("[CPU/Cond] 0xF is a reserved condition field", .{}),
     };
 }
 
@@ -650,15 +650,15 @@ fn getMode(bits: u5) ?Mode {
 }
 
 fn getModeChecked(cpu: *const Arm7tdmi, bits: u5) Mode {
-    return getMode(bits) orelse cpu.panic("[CPU|CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
+    return getMode(bits) orelse cpu.panic("[CPU/CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
 }
 
 fn armUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
     const id = armIdx(opcode);
-    cpu.panic("[CPU:ARM] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
+    cpu.panic("[CPU/Decode] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
 }
 
 fn thumbUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
     const id = thumbIdx(opcode);
-    cpu.panic("[CPU:THUMB] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
+    cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
 }

src/cpu/thumb/branch.zig

@@ -12,7 +12,7 @@ pub fn format16(comptime cond: u4) InstrFn {
             const offset = u32SignExtend(8, opcode & 0xFF) << 1;
 
             const should_execute = switch (cond) {
-                0xE, 0xF => cpu.panic("[CPU/THUMB] Undefined conditional branch with condition {}", .{cond}),
+                0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}),
                 else => checkCond(cpu.cpsr, cond),
             };
 

src/cpu/thumb/data_processing.zig

@@ -45,10 +45,7 @@ pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
                         break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
                     }
                 },
-                else => {
+                else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
-                    log.err("0b{b:0>2} is not a valid op", .{op});
-                    // TODO: Should we panic here?
-                },
             };
 
             // Equivalent to an ARM MOVS