feat: move thumb instr decoding to module
This commit is contained in:
243
src/core/cpu.zig
243
src/core/cpu.zig
@@ -16,7 +16,7 @@ const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
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const singleDataTransfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
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const halfAndSignedDataTransfer = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
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const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
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const branch = @import("cpu/arm/branch.zig").branch;
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const armBranch = @import("cpu/arm/branch.zig").branch;
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const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
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const armSoftwareInterrupt = @import("cpu/arm/software_interrupt.zig").armSoftwareInterrupt;
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const singleDataSwap = @import("cpu/arm/single_data_swap.zig").singleDataSwap;
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@@ -25,33 +25,126 @@ const multiply = @import("cpu/arm/multiply.zig").multiply;
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const multiplyLong = @import("cpu/arm/multiply.zig").multiplyLong;
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// THUMB Instruction Groups
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const format1 = @import("cpu/thumb/data_processing.zig").format1;
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const format2 = @import("cpu/thumb/data_processing.zig").format2;
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const format3 = @import("cpu/thumb/data_processing.zig").format3;
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const format12 = @import("cpu/thumb/data_processing.zig").format12;
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const format13 = @import("cpu/thumb/data_processing.zig").format13;
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const format4 = @import("cpu/thumb/alu.zig").format4;
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const format5 = @import("cpu/thumb/processing_branch.zig").format5;
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pub const thumb = struct {
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pub const InstrFn = fn (*Arm7tdmi, *Bus, u16) void;
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const lut: [0x400]InstrFn = populate();
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const format6 = @import("cpu/thumb/data_transfer.zig").format6;
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const format78 = @import("cpu/thumb/data_transfer.zig").format78;
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const format9 = @import("cpu/thumb/data_transfer.zig").format9;
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const format10 = @import("cpu/thumb/data_transfer.zig").format10;
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const format11 = @import("cpu/thumb/data_transfer.zig").format11;
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const format14 = @import("cpu/thumb/block_data_transfer.zig").format14;
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const format15 = @import("cpu/thumb/block_data_transfer.zig").format15;
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const processing = @import("cpu/thumb/data_processing.zig");
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const alu = @import("cpu/thumb/alu.zig").fmt4;
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const transfer = @import("cpu/thumb/data_transfer.zig");
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const block_transfer = @import("cpu/thumb/block_data_transfer.zig");
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const swi = @import("cpu/thumb/software_interrupt.zig").fmt17;
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const branch = @import("cpu/thumb/branch.zig");
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const format16 = @import("cpu/thumb/branch.zig").format16;
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const format18 = @import("cpu/thumb/branch.zig").format18;
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const format19 = @import("cpu/thumb/branch.zig").format19;
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/// Undefined THUMB Instruction Handler
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fn und(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const id = thumbIdx(opcode);
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cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
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}
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const thumbSoftwareInterrupt = @import("cpu/thumb/software_interrupt.zig").thumbSoftwareInterrupt;
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fn populate() [0x400]InstrFn {
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return comptime {
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@setEvalBranchQuota(5025); // This is exact
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var ret = [_]InstrFn{und} ** 0x400;
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var i: usize = 0;
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while (i < ret.len) : (i += 1) {
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ret[i] = switch (@as(u3, i >> 7 & 0x7)) {
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0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
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const I = i >> 4 & 1 == 1;
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const is_sub = i >> 3 & 1 == 1;
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const rn = i & 0x7;
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break :blk processing.fmt2(I, is_sub, rn);
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} else blk: {
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const op = i >> 5 & 0x3;
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const offset = i & 0x1F;
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break :blk processing.fmt1(op, offset);
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},
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0b001 => blk: {
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const op = i >> 5 & 0x3;
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const rd = i >> 2 & 0x7;
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break :blk processing.fmt3(op, rd);
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},
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0b010 => switch (@as(u2, i >> 5 & 0x3)) {
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0b00 => if (i >> 4 & 1 == 1) blk: {
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const op = i >> 2 & 0x3;
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const h1 = i >> 1 & 1;
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const h2 = i & 1;
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break :blk processing.fmt5(op, h1, h2);
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} else blk: {
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const op = i & 0xF;
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break :blk alu(op);
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},
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0b01 => blk: {
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const rd = i >> 2 & 0x7;
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break :blk transfer.fmt6(rd);
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},
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else => blk: {
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const op = i >> 4 & 0x3;
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const T = i >> 3 & 1 == 1;
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break :blk transfer.fmt78(op, T);
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},
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},
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0b011 => blk: {
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const B = i >> 6 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const offset = i & 0x1F;
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break :blk transfer.fmt9(B, L, offset);
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},
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else => switch (@as(u3, i >> 6 & 0x7)) {
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// MSB is guaranteed to be 1
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0b000 => blk: {
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const L = i >> 5 & 1 == 1;
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const offset = i & 0x1F;
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break :blk transfer.fmt10(L, offset);
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},
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0b001 => blk: {
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const L = i >> 5 & 1 == 1;
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const rd = i >> 2 & 0x7;
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break :blk transfer.fmt11(L, rd);
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},
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0b010 => blk: {
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const isSP = i >> 5 & 1 == 1;
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const rd = i >> 2 & 0x7;
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break :blk processing.fmt12(isSP, rd);
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},
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0b011 => if (i >> 4 & 1 == 1) blk: {
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const L = i >> 5 & 1 == 1;
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const R = i >> 2 & 1 == 1;
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break :blk block_transfer.fmt14(L, R);
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} else blk: {
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const S = i >> 1 & 1 == 1;
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break :blk processing.fmt13(S);
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},
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0b100 => blk: {
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const L = i >> 5 & 1 == 1;
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const rb = i >> 2 & 0x7;
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break :blk block_transfer.fmt15(L, rb);
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},
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0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
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break :blk thumb.swi();
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} else blk: {
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const cond = i >> 2 & 0xF;
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break :blk branch.fmt16(cond);
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},
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0b110 => branch.fmt18(),
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0b111 => blk: {
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const is_low = i >> 5 & 1 == 1;
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break :blk branch.fmt19(is_low);
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},
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},
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};
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}
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return ret;
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};
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}
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};
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pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
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const arm_lut: [0x1000]ArmInstrFn = armPopulate();
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const thumb_lut: [0x400]ThumbInstrFn = thumbPopulate();
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const enable_logging = false;
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const log = std.log.scoped(.Arm7Tdmi);
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@@ -260,7 +353,7 @@ pub const Arm7tdmi = struct {
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const opcode = self.fetch(u16);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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thumb_lut[thumbIdx(opcode)](self, &self.bus, opcode);
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thumb.lut[thumbIdx(opcode)](self, &self.bus, opcode);
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} else {
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const opcode = self.fetch(u32);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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@@ -497,105 +590,6 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
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};
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}
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fn thumbPopulate() [0x400]ThumbInstrFn {
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return comptime {
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@setEvalBranchQuota(5025); // This is exact
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var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
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var i: usize = 0;
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while (i < lut.len) : (i += 1) {
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lut[i] = switch (@as(u3, i >> 7 & 0x7)) {
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0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
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const I = i >> 4 & 1 == 1;
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const is_sub = i >> 3 & 1 == 1;
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const rn = i & 0x7;
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break :blk format2(I, is_sub, rn);
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} else blk: {
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const op = i >> 5 & 0x3;
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const offset = i & 0x1F;
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break :blk format1(op, offset);
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},
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0b001 => blk: {
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const op = i >> 5 & 0x3;
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const rd = i >> 2 & 0x7;
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break :blk format3(op, rd);
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},
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0b010 => switch (@as(u2, i >> 5 & 0x3)) {
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0b00 => if (i >> 4 & 1 == 1) blk: {
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const op = i >> 2 & 0x3;
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const h1 = i >> 1 & 1;
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const h2 = i & 1;
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break :blk format5(op, h1, h2);
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} else blk: {
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const op = i & 0xF;
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break :blk format4(op);
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},
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0b01 => blk: {
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const rd = i >> 2 & 0x7;
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break :blk format6(rd);
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},
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else => blk: {
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const op = i >> 4 & 0x3;
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const T = i >> 3 & 1 == 1;
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break :blk format78(op, T);
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},
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},
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0b011 => blk: {
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const B = i >> 6 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const offset = i & 0x1F;
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break :blk format9(B, L, offset);
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},
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else => switch (@as(u3, i >> 6 & 0x7)) {
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// MSB is guaranteed to be 1
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0b000 => blk: {
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const L = i >> 5 & 1 == 1;
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const offset = i & 0x1F;
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break :blk format10(L, offset);
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},
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0b001 => blk: {
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const L = i >> 5 & 1 == 1;
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const rd = i >> 2 & 0x7;
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break :blk format11(L, rd);
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},
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0b010 => blk: {
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const isSP = i >> 5 & 1 == 1;
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const rd = i >> 2 & 0x7;
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break :blk format12(isSP, rd);
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},
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0b011 => if (i >> 4 & 1 == 1) blk: {
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const L = i >> 5 & 1 == 1;
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const R = i >> 2 & 1 == 1;
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break :blk format14(L, R);
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} else blk: {
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const S = i >> 1 & 1 == 1;
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break :blk format13(S);
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},
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0b100 => blk: {
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const L = i >> 5 & 1 == 1;
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const rb = i >> 2 & 0x7;
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break :blk format15(L, rb);
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},
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0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
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break :blk thumbSoftwareInterrupt();
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} else blk: {
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const cond = i >> 2 & 0xF;
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break :blk format16(cond);
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},
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0b110 => format18(),
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0b111 => blk: {
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const is_low = i >> 5 & 1 == 1;
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break :blk format19(is_low);
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},
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},
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};
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}
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return lut;
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};
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}
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fn armPopulate() [0x1000]ArmInstrFn {
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return comptime {
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@setEvalBranchQuota(0xE000);
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@@ -657,7 +651,7 @@ fn armPopulate() [0x1000]ArmInstrFn {
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},
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0b01 => blk: {
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const L = i >> 8 & 1 == 1;
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break :blk branch(L);
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break :blk armBranch(L);
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},
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0b10 => armUndefined, // COP Data Transfer
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0b11 => if (i >> 8 & 1 == 1) armSoftwareInterrupt() else armUndefined, // COP Data Operation + Register Transfer
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@@ -708,8 +702,3 @@ fn armUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const id = armIdx(opcode);
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cpu.panic("[CPU/Decode] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
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}
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fn thumbUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const id = thumbIdx(opcode);
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cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
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}
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