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feat: working pipeline implementation

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-09-28 16:11:25 -03:00
parent 5bb5bdf389
commit 870e991862
10 changed files with 31 additions and 45 deletions
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4
src/core/cpu/arm/block_data_transfer.zig
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@@ -55,7 +55,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
if (L) {
cpu.r[15] = bus.read(u32, und_addr);
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
} else {
// FIXME: Should r15 on write be +12 ahead?
bus.write(u32, und_addr, cpu.r[15] + 4);
@@ -92,7 +92,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
cpu.r[i] = value;
if (i == 0xF) {
cpu.r[i] &= ~@as(u32, 3); // Align r15
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
if (S) cpu.setCpsr(cpu.spsr.raw);
}

4
src/core/cpu/arm/branch.zig
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@@ -12,7 +12,7 @@ pub fn branch(comptime L: bool) InstrFn {
if (L) cpu.r[14] = cpu.r[15] - 4;
cpu.r[15] +%= sext(u32, u24, opcode) << 2;
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
}
}.inner;
}
@@ -24,5 +24,5 @@ pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
cpu.cpsr.t.write(thumb);
if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
}

7
src/core/cpu/arm/data_processing.zig
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@@ -76,9 +76,8 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
else => {
cpu.r[rd] = result;
if (rd == 0xF) {
if (S) cpu.setCpsrNoFlush(cpu.spsr.raw);
cpu.pipe.reload(u32, cpu);
if (S) cpu.setCpsr(cpu.spsr.raw);
cpu.pipe.reload(cpu);
}
},
}
@@ -180,5 +179,5 @@ pub fn adc(overflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
@setCold(true);
cpu.setCpsrNoFlush(cpu.spsr.raw);
cpu.setCpsr(cpu.spsr.raw);
}

4
src/core/cpu/arm/single_data_transfer.zig
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@@ -47,13 +47,13 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
address = modified_base;
if (W and P or !P) {
cpu.r[rn] = address;
if (rn == 0xF) cpu.pipe.reload(u32, cpu);
if (rn == 0xF) cpu.pipe.reload(cpu);
}
if (L) {
// This emulates the LDR rd == rn behaviour
cpu.r[rd] = result;
if (rd == 0xF) cpu.pipe.reload(u32, cpu);
if (rd == 0xF) cpu.pipe.reload(cpu);
}
}
}.inner;

2
src/core/cpu/arm/software_interrupt.zig
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@@ -17,7 +17,7 @@ pub fn armSoftwareInterrupt() InstrFn {
cpu.r[14] = ret_addr; // Resume Execution
cpu.spsr.raw = cpsr; // Previous mode CPSR
cpu.r[15] = 0x0000_0008;
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
}
}.inner;
}