fix: don't flush pipeline when reloading CPSR in ARM Data Processing
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parent
dd4bb4ff03
commit
84ccb7224b
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@ -34,8 +34,8 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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0x3 => result = op2 -% op1, // RSB
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0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
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0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
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0x6 => result = newSbc(op1, op2, old_carry), // SBC
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0x7 => result = newSbc(op2, op1, old_carry), // RSC
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0x6 => result = sbc(op1, op2, old_carry), // SBC
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0x7 => result = sbc(op2, op1, old_carry), // RSC
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0x8 => {
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// TST
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if (rd == 0xF)
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@ -76,7 +76,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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else => {
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cpu.r[rd] = result;
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if (rd == 0xF) {
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if (S) cpu.setCpsr(cpu.spsr.raw);
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if (S) cpu.setCpsrNoFlush(cpu.spsr.raw);
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cpu.pipe.reload(u32, cpu);
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}
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@ -145,7 +145,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// TEST, TEQ specific
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// TST, TEQ specific
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = execute(true, cpu, opcode);
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}
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@ -155,134 +155,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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}.inner;
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}
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// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
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// return struct {
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// fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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// const rd = @truncate(u4, opcode >> 12 & 0xF);
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// const rn = opcode >> 16 & 0xF;
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// const old_carry = @boolToInt(cpu.cpsr.c.read());
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// // If certain conditions are met, PC is 12 ahead instead of 8
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// // TODO: What are these conditions? I can't remember
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// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
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// const op1 = cpu.r[rn];
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// const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
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// const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
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// // Undo special condition from above
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// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
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// switch (instrKind) {
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// 0x0 => {
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// // AND
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// const result = op1 & op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0x1 => {
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// // EOR
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// const result = op1 ^ op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0x2 => {
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// // SUB
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// cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
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// },
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// 0x3 => {
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// // RSB
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// cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
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// },
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// 0x4 => {
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// // ADD
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// cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
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// },
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// 0x5 => {
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// // ADC
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// cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
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// },
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// 0x6 => {
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// // SBC
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// cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
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// },
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// 0x7 => {
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// // RSC
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// cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
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// },
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// 0x8 => {
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// // TST
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// const result = op1 & op2;
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// setTestOpFlags(S, cpu, opcode, result);
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// },
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// 0x9 => {
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// // TEQ
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// const result = op1 ^ op2;
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// setTestOpFlags(S, cpu, opcode, result);
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// },
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// 0xA => {
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// // CMP
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// cmp(cpu, op1, op2);
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// },
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// 0xB => {
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// // CMN
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// if (rd == 0xF)
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// return undefinedTestBehaviour(cpu);
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// cmn(cpu, op1, op2);
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// },
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// 0xC => {
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// // ORR
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// const result = op1 | op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0xD => {
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// // MOV
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// cpu.r[rd] = op2;
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// setArmLogicOpFlags(S, cpu, rd, op2);
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// },
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// 0xE => {
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// // BIC
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// const result = op1 & ~op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// 0xF => {
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// // MVN
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// const result = ~op2;
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// cpu.r[rd] = result;
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// setArmLogicOpFlags(S, cpu, rd, result);
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// },
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// }
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// if (rd == 0xF) cpu.pipe.reload(u32, cpu);
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// }
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// }.inner;
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// }
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fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = sbc(false, cpu, left, right, old_carry);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = sbc(S, cpu, left, right, old_carry);
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}
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return result;
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}
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fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
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pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
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// TODO: Make your own version (thanks peach.bot)
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const subtrahend = @as(u64, right) -% old_carry +% 1;
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const ret = @truncate(u32, left -% subtrahend);
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@ -290,33 +163,6 @@ fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
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return ret;
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}
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pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
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// TODO: Make your own version (thanks peach.bot)
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const subtrahend = @as(u64, right) -% old_carry +% 1;
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const result = @truncate(u32, left -% subtrahend);
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(subtrahend <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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fn armSub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = sub(false, cpu, left, right);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = sub(S, cpu, left, right);
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}
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return result;
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}
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pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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const result = left -% right;
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@ -330,18 +176,6 @@ pub fn sub(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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return result;
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}
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fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = add(false, cpu, left, right);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = add(S, cpu, left, right);
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}
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return result;
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}
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fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
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var ret: u32 = undefined;
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didOverflow.* = @addWithOverflow(u32, left, right, &ret);
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@ -362,19 +196,7 @@ pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
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return result;
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}
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fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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if (S and rd == 0xF) {
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result = adc(false, cpu, left, right, old_carry);
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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result = adc(S, cpu, left, right, old_carry);
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}
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return result;
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}
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fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
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pub fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
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var ret: u32 = undefined;
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const did = @addWithOverflow(u32, left, right, &ret);
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const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
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@ -383,21 +205,6 @@ fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
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return ret;
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}
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pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
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var result: u32 = undefined;
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const did = @addWithOverflow(u32, left, right, &result);
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const overflow = @addWithOverflow(u32, result, old_carry, &result);
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(did or overflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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return result;
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}
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pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
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const result = left -% right;
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@ -407,24 +214,6 @@ pub fn cmp(cpu: *Arm7tdmi, left: u32, right: u32) void {
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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pub fn cmn(cpu: *Arm7tdmi, left: u32, right: u32) void {
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, left, right, &result);
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((left ^ result) & (right ^ result)) >> 31 & 1 == 1);
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}
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fn setArmLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
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if (S and rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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setLogicOpFlags(S, cpu, result);
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}
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}
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pub fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void {
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if (S) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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@ -433,13 +222,6 @@ pub fn setLogicOpFlags(comptime S: bool, cpu: *Arm7tdmi, result: u32) void {
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}
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}
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fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = execute(true, cpu, opcode);
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}
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fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
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@setCold(true);
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cpu.setCpsrNoFlush(cpu.spsr.raw);
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@ -2,18 +2,13 @@ const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const adc = @import("../arm/data_processing.zig").adc;
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const adc = @import("../arm/data_processing.zig").newAdc;
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const sbc = @import("../arm/data_processing.zig").sbc;
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const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const cmn = @import("../arm/data_processing.zig").cmn;
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const setTestOpFlags = @import("../arm/data_processing.zig").setTestOpFlags;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const logicalLeft = @import("../barrel_shifter.zig").logicalLeft;
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const logicalRight = @import("../barrel_shifter.zig").logicalRight;
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const arithmeticRight = @import("../barrel_shifter.zig").arithmeticRight;
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const rotateRight = @import("../barrel_shifter.zig").rotateRight;
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const lsl = @import("../barrel_shifter.zig").logicalLeft;
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const lsr = @import("../barrel_shifter.zig").logicalRight;
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const asr = @import("../barrel_shifter.zig").arithmeticRight;
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const ror = @import("../barrel_shifter.zig").rotateRight;
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pub fn fmt4(comptime op: u4) InstrFn {
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return struct {
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@ -22,96 +17,84 @@ pub fn fmt4(comptime op: u4) InstrFn {
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const rd = opcode & 0x7;
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const carry = @boolToInt(cpu.cpsr.c.read());
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var result: u32 = undefined;
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var didOverflow: bool = undefined;
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switch (op) {
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0x0 => {
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// AND
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const result = cpu.r[rd] & cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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0x0 => result = cpu.r[rd] & cpu.r[rs], // AND
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0x1 => result = cpu.r[rd] ^ cpu.r[rs], // EOR
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0x2 => result = lsl(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // LSL
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0x3 => result = lsr(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // LSR
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0x4 => result = asr(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // ASR
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0x5 => result = adc(&didOverflow, cpu.r[rd], cpu.r[rs], carry), // ADC
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0x6 => result = sbc(cpu.r[rd], cpu.r[rs], carry), // SBC
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0x7 => result = ror(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // ROR
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0x8 => result = cpu.r[rd] & cpu.r[rs], // TST
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0x9 => result = 0 -% cpu.r[rs], // NEG
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0xA => result = cpu.r[rd] -% cpu.r[rs], // CMP
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0xB => didOverflow = @addWithOverflow(u32, cpu.r[rd], cpu.r[rs], &result), // CMN
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0xC => result = cpu.r[rd] | cpu.r[rs], // ORR
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0xD => result = @truncate(u32, @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd])),
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0xE => result = cpu.r[rd] & ~cpu.r[rs],
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0xF => result = ~cpu.r[rs],
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}
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// Write to Destination Register
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switch (op) {
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0x8, 0xA, 0xB => {},
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else => cpu.r[rd] = result,
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}
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// Write Flags
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switch (op) {
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0x0, 0x1, 0x2, 0x3, 0x4, 0x7, 0xC, 0xE, 0xF => {
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// Logic Operations
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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},
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0x1 => {
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// EOR
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const result = cpu.r[rd] ^ cpu.r[rs];
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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0x8, 0xA => {
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// Test Flags
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// CMN (0xB) is handled with ADC
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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if (op == 0xA) {
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// CMP specific
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cpu.cpsr.c.write(cpu.r[rs] <= cpu.r[rd]);
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cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
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}
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},
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0x2 => {
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// LSL
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const result = logicalLeft(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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},
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0x3 => {
|
||||
// LSR
|
||||
const result = logicalRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x4 => {
|
||||
// ASR
|
||||
const result = arithmeticRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x5 => {
|
||||
// ADC
|
||||
cpu.r[rd] = adc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
|
||||
0x5, 0xB => {
|
||||
// ADC, CMN
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(didOverflow);
|
||||
cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (cpu.r[rs] ^ result)) >> 31 & 1 == 1);
|
||||
|
||||
// FIXME: Pretty sure CMN Is the same
|
||||
},
|
||||
0x6 => {
|
||||
// SBC
|
||||
cpu.r[rd] = sbc(true, cpu, cpu.r[rd], cpu.r[rs], carry);
|
||||
},
|
||||
0x7 => {
|
||||
// ROR
|
||||
const result = rotateRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0x8 => {
|
||||
// TST
|
||||
const result = cpu.r[rd] & cpu.r[rs];
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
const subtrahend = @as(u64, cpu.r[rs]) -% carry +% 1;
|
||||
cpu.cpsr.c.write(subtrahend <= cpu.r[rd]);
|
||||
cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
|
||||
},
|
||||
0x9 => {
|
||||
// NEG
|
||||
cpu.r[rd] = sub(true, cpu, 0, cpu.r[rs]);
|
||||
},
|
||||
0xA => {
|
||||
// CMP
|
||||
cmp(cpu, cpu.r[rd], cpu.r[rs]);
|
||||
},
|
||||
0xB => {
|
||||
// CMN
|
||||
cmn(cpu, cpu.r[rd], cpu.r[rs]);
|
||||
},
|
||||
0xC => {
|
||||
// ORR
|
||||
const result = cpu.r[rd] | cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(cpu.r[rs] <= 0);
|
||||
cpu.cpsr.v.write(((0 ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
|
||||
},
|
||||
0xD => {
|
||||
// MUL
|
||||
const temp = @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd]);
|
||||
const result = @truncate(u32, temp);
|
||||
cpu.r[rd] = result;
|
||||
|
||||
// Multiplication
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
// V is unaffected, assuming similar behaviour to ARMv4 MUL C is undefined
|
||||
},
|
||||
0xE => {
|
||||
// BIC
|
||||
const result = cpu.r[rd] & ~cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
0xF => {
|
||||
// MVN
|
||||
const result = ~cpu.r[rs];
|
||||
cpu.r[rd] = result;
|
||||
setLogicOpFlags(true, cpu, result);
|
||||
},
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
|
|
|||
Loading…
Reference in New Issue