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chore: reimplement bus read/writes

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 16:48:43 -03:00
parent 37a360ec07
commit 80e714e2eb
11 changed files with 130 additions and 166 deletions
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3
src/ppu.zig
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@@ -457,6 +457,7 @@ const Palette = struct {
self.buf[addr + 1] = @truncate(u8, value >> 8);
self.buf[addr + 0] = @truncate(u8, value >> 0);
},
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
else => @compileError("PALRAM: Unsupported write width"),
}
}
@@ -511,6 +512,7 @@ const Vram = struct {
self.buf[addr + 1] = @truncate(u8, value >> 8);
self.buf[addr + 0] = @truncate(u8, value >> 0);
},
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
else => @compileError("VRAM: Unsupported write width"),
}
}
@@ -566,6 +568,7 @@ const Oam = struct {
self.buf[addr + 1] = @truncate(u8, value >> 8);
self.buf[addr + 0] = @truncate(u8, value >> 0);
},
u8 => log.err("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
else => @compileError("OAM: Unsupported write width"),
}
}