chore: reimplement bus read/writes
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								src/cpu.zig
									
									
									
									
									
								
							
							
						
						
									
										10
									
								
								src/cpu.zig
									
									
									
									
									
								
							@@ -306,12 +306,12 @@ pub const Arm7tdmi = struct {
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    fn thumbFetch(self: *Self) u16 {
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        defer self.r[15] += 2;
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        return self.bus.read16(self.r[15]);
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        return self.bus.read(u16, self.r[15]);
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    }
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    fn fetch(self: *Self) u32 {
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        defer self.r[15] += 4;
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        return self.bus.read32(self.r[15]);
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        return self.bus.read(u32, self.r[15]);
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    }
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    pub fn fakePC(self: *const Self) u32 {
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@@ -341,11 +341,11 @@ pub const Arm7tdmi = struct {
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        prettyPrintPsr(&self.spsr);
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        if (self.cpsr.t.read()) {
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            const opcode = self.bus.read16(self.r[15] - 4);
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            const opcode = self.bus.read(u16, self.r[15] - 4);
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            const id = thumbIdx(opcode);
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            std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
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        } else {
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            const opcode = self.bus.read32(self.r[15] - 4);
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            const opcode = self.bus.read(u32, self.r[15] - 4);
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            const id = armIdx(opcode);
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            std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
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        }
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@@ -432,7 +432,7 @@ pub const Arm7tdmi = struct {
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        if (self.cpsr.t.read()) {
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            if (opcode >> 11 == 0x1E) {
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                // Instruction 1 of a BL Opcode, print in ARM mode
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                const tmp_opcode = self.bus.read32(self.r[15] - 2);
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                const tmp_opcode = self.bus.read(u32, self.r[15] - 2);
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                const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16;
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                log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
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            } else {
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