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chore: reimplement bus read/writes

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 16:48:43 -03:00
parent 37a360ec07
commit 80e714e2eb
11 changed files with 130 additions and 166 deletions
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8
src/cpu/arm/single_data_transfer.zig
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@@ -31,21 +31,21 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
if (L) {
if (B) {
// LDRB
result = bus.read8(address);
result = bus.read(u8, address);
} else {
// LDR
const value = bus.read32(address);
const value = bus.read(u32, address);
result = rotr(u32, value, 8 * (address & 0x3));
}
} else {
if (B) {
// STRB
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write8(address, @truncate(u8, value));
bus.write(u8, address, @truncate(u8, value));
} else {
// STR
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write32(address, value);
bus.write(u32, address, value);
}
}