fix(cpu): resolve off-by-one error when executing LDM
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@ -12,9 +12,10 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
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if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
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if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
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var address: u32 = undefined;
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if (U) {
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if (U) {
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// Increment
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// Increment
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var address = if (P) base + 4 else base;
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address = if (P) base + 4 else base;
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var i: u5 = 0;
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var i: u5 = 0;
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while (i < 0x10) : (i += 1) {
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while (i < 0x10) : (i += 1) {
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@ -23,24 +24,22 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
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address += 4;
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address += 4;
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}
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}
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}
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}
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if (W and P or !P) cpu.r[rn] = address - 4;
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} else {
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} else {
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// Decrement
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// Decrement
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var address = if (P) base - 4 else base;
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address = if (P) base - 4 else base;
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var i: u5 = 0x10;
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var i: u5 = 0x10;
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while (i > 0) : (i -= 1) {
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while (i > 0) : (i -= 1) {
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const reg_idx = i - 1;
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const j = i - 1;
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if (opcode >> reg_idx & 1 == 1) {
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if (opcode >> j & 1 == 1) {
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transfer(cpu, bus, reg_idx, address);
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transfer(cpu, bus, j, address);
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address -= 4;
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address -= 4;
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}
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}
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}
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}
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if (W and P or !P) cpu.r[rn] = address + 4;
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}
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}
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if (W and P or !P) cpu.r[rn] = if (U) address else address + 4;
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}
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}
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fn transfer(cpu: *Arm7tdmi, bus: *Bus, i: u5, address: u32) void {
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fn transfer(cpu: *Arm7tdmi, bus: *Bus, i: u5, address: u32) void {
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