feat(cpu): stub PSR Transfer instructions
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@ -8,6 +8,7 @@ const Bitfield = @import("bitfield").Bitfield;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const dataProcessing = @import("cpu/data_processing.zig").dataProcessing;
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const dataProcessing = @import("cpu/data_processing.zig").dataProcessing;
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const psrTransfer = @import("cpu/psr_transfer.zig").psrTransfer;
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const singleDataTransfer = @import("cpu/single_data_transfer.zig").singleDataTransfer;
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const singleDataTransfer = @import("cpu/single_data_transfer.zig").singleDataTransfer;
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const halfAndSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
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const halfAndSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
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const blockDataTransfer = @import("cpu/block_data_transfer.zig").blockDataTransfer;
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const blockDataTransfer = @import("cpu/block_data_transfer.zig").blockDataTransfer;
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@ -133,6 +134,14 @@ fn populate() [0x1000]InstrFn {
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lut[i] = dataProcessing(I, S, instrKind);
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lut[i] = dataProcessing(I, S, instrKind);
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}
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}
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if (i >> 10 & 0x3 == 0b00 and i >> 7 & 0x3 == 0b10 and i >> 4 & 1 == 0) {
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// PSR Transfer
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const I = i >> 9 & 1 == 1;
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const isSpsr = i >> 6 & 1 == 1;
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lut[i] = psrTransfer(I, isSpsr);
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}
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if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
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if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
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const P = i >> 8 & 1 == 1;
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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@ -0,0 +1,13 @@
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const std = @import("std");
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const Bus = @import("../Bus.zig");
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../cpu.zig").InstrFn;
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pub fn psrTransfer(comptime _: bool, comptime _: bool) InstrFn {
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return struct {
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fn inner(_: *Arm7tdmi, _: *Bus, _: u32) void {
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std.debug.panic("[CPU] TODO: Implement PSR Transfer Instructions", .{});
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}
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}.inner;
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}
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