chore: mess with debug statements + mask APU I/O reads
This commit is contained in:
parent
708f64035f
commit
7441af9582
72
src/apu.zig
72
src/apu.zig
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@ -9,6 +9,8 @@ const SoundFifo = std.fifo.LinearFifo(u8, .{ .Static = 0x20 });
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const AudioDeviceId = SDL.SDL_AudioDeviceID;
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const intToBytes = @import("util.zig").intToBytes;
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const readUndefined = @import("util.zig").readUndefined;
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const writeUndefined = @import("util.zig").writeUndefined;
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const log = std.log.scoped(.APU);
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pub const host_sample_rate = 1 << 15;
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@ -18,25 +20,28 @@ pub fn read(comptime T: type, apu: *const Apu, addr: u32) T {
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return switch (T) {
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u16 => switch (byte) {
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0x60 => apu.ch1.sweep.raw, // SOUND1CNT_L
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0x60 => apu.ch1.getSoundCntL(),
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0x62 => apu.ch1.getSoundCntH(),
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0x64 => apu.ch1.freq.raw, // SOUND1CNT_X
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0x64 => apu.ch1.getSoundCntX(),
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0x68 => apu.ch2.getSoundCntL(),
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0x6C => apu.ch2.freq.raw, // SOUND2CNT_H
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0x6C => apu.ch2.getSoundCntH(),
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0x70 => apu.ch3.select.raw, // SOUND3CNT_L
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0x74 => apu.ch3.freq.raw, // SOUND3CNT_X
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0x70 => apu.ch3.select.raw & 0xE0, // SOUND3CNT_L
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0x72 => apu.ch3.getSoundCntH(),
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0x74 => apu.ch3.freq.raw & 0x4000, // SOUND3CNT_X
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0x78 => apu.ch4.getSoundCntL(),
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0x7C => apu.ch4.getSoundCntH(),
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0x80 => apu.dma_cnt.raw, // SOUNDCNT_L
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0x80 => apu.psg_cnt.raw & 0xFF77, // SOUNDCNT_L
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0x82 => apu.dma_cnt.raw & 0x770F, // SOUNDCNT_H
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0x84 => apu.getSoundCntX(),
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0x88 => apu.bias.raw, // SOUNDBIAS
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else => @panic("TODO: Unexpected APU u16 read"),
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0x90...0x9F => apu.ch3.wave_dev.read(T, apu.ch3.select, addr),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u8 => switch (byte) {
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0x60 => apu.ch1.sweep.raw, // NR10
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0x60 => apu.ch1.getSoundCntL(), // NR10
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0x63 => apu.ch1.envelope.raw, // NR12
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0x69 => apu.ch2.envelope.raw, // NR22
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0x73 => apu.ch3.vol.raw, // NR32
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@ -45,9 +50,9 @@ pub fn read(comptime T: type, apu: *const Apu, addr: u32) T {
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0x81 => @truncate(u8, apu.psg_cnt.raw >> 8), // NR51
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0x84 => apu.getSoundCntX(),
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0x89 => @truncate(u8, apu.bias.raw >> 8), // SOUNDBIAS_H
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else => @panic("TODO: Unexpected APU u8 read"),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u32 => @panic("TODO: Unexpected APU u32 read"),
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u32 => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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else => @compileError("APU: Unsupported read width"),
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};
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}
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@ -65,7 +70,7 @@ pub fn write(comptime T: type, apu: *Apu, addr: u32, value: T) void {
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0x90...0x9F => apu.ch3.wave_dev.write(T, apu.ch3.select, addr, value),
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0xA0 => apu.chA.push(value), // FIFO_A
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0xA4 => apu.chB.push(value), // FIFO_B
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else => @panic("TODO: Unexpected APU u32 write"),
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else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u16 => switch (byte) {
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0x60 => apu.ch1.sweep.raw = @truncate(u8, value), // SOUND1CNT_L
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@ -88,7 +93,7 @@ pub fn write(comptime T: type, apu: *Apu, addr: u32, value: T) void {
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0x88 => apu.bias.raw = value, // SOUNDBIAS
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// WAVE_RAM
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0x90...0x9F => apu.ch3.wave_dev.write(T, apu.ch3.select, addr, value),
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else => @panic("TODO: Unexpected APU u16 write"),
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else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u8 => switch (byte) {
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0x60 => apu.ch1.sweep.raw = value, // NR10
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@ -118,7 +123,7 @@ pub fn write(comptime T: type, apu: *Apu, addr: u32, value: T) void {
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0x84 => apu.setSoundCntX(value >> 7 & 1 == 1), // NR52
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0x89 => apu.setSoundBiasH(value),
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0x90...0x9F => apu.ch3.wave_dev.write(T, apu.ch3.select, addr, value),
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else => @panic("TODO: Unexpected APU u8 write"),
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else => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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else => @compileError("APU: Unsupported write width"),
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}
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@ -500,9 +505,14 @@ const ToneSweep = struct {
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return @as(i16, self.sample);
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}
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/// NR10
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pub fn getSoundCntL(self: *const Self) u8 {
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return self.sweep.raw & 0x7F;
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}
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/// NR11, NR12
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pub fn getSoundCntH(self: *const Self) u16 {
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return @as(u16, self.envelope.raw) << 8 | self.duty.raw;
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return @as(u16, self.envelope.raw) << 8 | (self.duty.raw & 0xC0);
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}
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/// NR11, NR12
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@ -523,6 +533,11 @@ const ToneSweep = struct {
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if (!self.isDacEnabled()) self.enabled = false;
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}
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/// NR13, NR14
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pub fn getSoundCntX(self: *const Self) u16 {
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return self.freq.raw & 0x4000;
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}
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/// NR13, NR14
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pub fn setSoundCntX(self: *Self, fs: *const FrameSequencer, value: u16) void {
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self.setNr13(@truncate(u8, value));
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@ -641,7 +656,7 @@ const Tone = struct {
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/// NR21, NR22
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pub fn getSoundCntL(self: *const Self) u16 {
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return @as(u16, self.envelope.raw) << 8 | self.duty.raw;
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return @as(u16, self.envelope.raw) << 8 | (self.duty.raw & 0xC0);
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}
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/// NR21, NR22
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@ -662,6 +677,11 @@ const Tone = struct {
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if (!self.isDacEnabled()) self.enabled = false;
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}
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/// NR23, NR24
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pub fn getSoundCntH(self: *const Self) u16 {
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return self.freq.raw & 0x4000;
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}
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/// NR23, NR24
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pub fn setSoundCntH(self: *Self, fs: *const FrameSequencer, value: u16) void {
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self.setNr23(@truncate(u8, value));
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@ -759,6 +779,11 @@ const Wave = struct {
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if (!self.select.enabled.read()) self.enabled = false;
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}
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/// NR31, NR32
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fn getSoundCntH(self: *const Self) u16 {
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return @as(u16, self.length & 0xE0) << 8;
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}
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/// NR31, NR32
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pub fn setSoundCntH(self: *Self, value: u16) void {
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self.setNr31(@truncate(u8, value));
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@ -880,7 +905,7 @@ const Noise = struct {
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/// NR41, NR42
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pub fn getSoundCntL(self: *const Self) u16 {
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return @as(u16, self.envelope.raw) << 8 | self.len;
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return @as(u16, self.envelope.raw) << 8;
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}
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/// NR41, NR42
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@ -903,7 +928,7 @@ const Noise = struct {
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/// NR43, NR44
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pub fn getSoundCntH(self: *const Self) u16 {
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return @as(u16, self.poly.raw) << 8 | self.cnt.raw;
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return @as(u16, self.poly.raw & 0x40) << 8 | self.cnt.raw;
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}
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/// NR43, NR44
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@ -1143,10 +1168,15 @@ const WaveDevice = struct {
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const base = if (!cnt.bank.read()) @as(u32, 0x10) else 0; // Write to the Opposite Bank in Use
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const i = base + addr - 0x0400_0090;
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switch (T) {
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u32, u16, u8 => std.mem.writeIntSliceLittle(T, self.buf[i..][0..@sizeOf(T)], value),
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else => @compileError("Ch3 WAVERAM: Unsupported write width"),
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std.mem.writeIntSliceLittle(T, self.buf[i..][0..@sizeOf(T)], value);
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}
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fn read(self: *const Self, comptime T: type, cnt: io.WaveSelect, addr: u32) T {
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// TODO: Handle reads when Channel 3 is disabled
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const base = if (!cnt.bank.read()) @as(u32, 0x10) else 0; // Read from the Opposite Bank in Use
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const i = base + addr - 0x0400_0090;
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return std.mem.readIntSliceLittle(T, self.buf[i..][0..@sizeOf(T)]);
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}
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};
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@ -123,7 +123,7 @@ pub fn write(self: *Self, comptime T: type, word_count: u16, address: u32, value
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0x0800_00C8 => log.err("Wrote {} 0x{X:} to I/O Port Control", .{ T, value }),
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else => {},
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},
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u8 => log.warn("Wrote {} 0x{X:} to 0x{X:0>8}, Ignored.", .{ T, value, address }),
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u8 => log.debug("Wrote {} 0x{X:} to 0x{X:0>8}, Ignored.", .{ T, value, address }),
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else => @compileError("GamePak: Unsupported write width"),
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}
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}
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@ -4,6 +4,8 @@ const DmaControl = @import("io.zig").DmaControl;
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const Bus = @import("../Bus.zig");
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const readUndefined = @import("../util.zig").readUndefined;
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const writeUndefined = @import("../util.zig").writeUndefined;
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pub const DmaTuple = std.meta.Tuple(&[_]type{ DmaController(0), DmaController(1), DmaController(2), DmaController(3) });
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const log = std.log.scoped(.DmaTransfer);
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@ -20,16 +22,16 @@ pub fn read(comptime T: type, dma: *const DmaTuple, addr: u32) T {
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0xC4 => @as(T, dma.*[1].cnt.raw) << 16,
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0xD0 => @as(T, dma.*[1].cnt.raw) << 16,
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0xDC => @as(T, dma.*[3].cnt.raw) << 16,
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else => @panic("TODO: Unexpected u32 DMA read"),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u16 => switch (byte) {
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0xBA => dma.*[0].cnt.raw,
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0xC6 => dma.*[1].cnt.raw,
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0xD2 => dma.*[2].cnt.raw,
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0xDE => dma.*[3].cnt.raw,
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else => @panic("TODO: Unexpected u16 DMA read"),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u8 => @panic("TODO: Unexpected u8 DMA read"),
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u8 => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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else => @compileError("DMA: Unsupported read width"),
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};
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}
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@ -51,7 +53,7 @@ pub fn write(comptime T: type, dma: *DmaTuple, addr: u32, value: T) void {
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0xD4 => dma.*[3].setSad(value),
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0xD8 => dma.*[3].setDad(value),
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0xDC => dma.*[3].setCnt(value),
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else => @panic("TODO: Unexpected u32 DMA write"),
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else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u16 => switch (byte) {
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0xB0 => dma.*[0].setSad(setU32L(dma.*[0].sad, value)),
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@ -81,9 +83,9 @@ pub fn write(comptime T: type, dma: *DmaTuple, addr: u32, value: T) void {
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0xDA => dma.*[3].setDad(setU32H(dma.*[3].dad, value)),
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0xDC => dma.*[3].setCntL(value),
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0xDE => dma.*[3].setCntH(value),
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else => @panic("TODO: Unexpected u16 DMA write"),
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else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u8 => @panic("TODO: Unexpected u8 DMA write"),
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u8 => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
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else => @compileError("DMA: Unsupported write width"),
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}
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}
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@ -11,6 +11,8 @@ const timer = @import("timer.zig");
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const dma = @import("dma.zig");
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const apu = @import("../apu.zig");
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const readUndefined = @import("../util.zig").readUndefined;
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const writeUndefined = @import("../util.zig").writeUndefined;
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const log = std.log.scoped(.@"I/O");
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pub const Io = struct {
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@ -56,18 +58,18 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_0100...0x0400_010C => timer.read(T, &bus.tim, address),
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// Serial Communication 1
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0x0400_0128 => unimplementedRead("Read {} from SIOCNT and SIOMLT_SEND", .{T}),
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0x0400_0128 => readTodo("Read {} from SIOCNT and SIOMLT_SEND", .{T}),
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// Keypad Input
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0x0400_0130 => unimplementedRead("Read {} from KEYINPUT", .{T}),
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0x0400_0130 => readTodo("Read {} from KEYINPUT", .{T}),
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// Serial Communication 2
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0x0400_0150 => unimplementedRead("Read {} from JOY_RECV", .{T}),
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0x0400_0150 => readTodo("Read {} from JOY_RECV", .{T}),
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// Interrupts
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0x0400_0200 => @as(T, bus.io.irq.raw) << 16 | bus.io.ie.raw,
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0x0400_0208 => @boolToInt(bus.io.ime),
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else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
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},
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u16 => switch (address) {
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// Display
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@ -78,10 +80,10 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_000A => bus.ppu.bg[1].cnt.raw,
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0x0400_000C => bus.ppu.bg[2].cnt.raw,
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0x0400_000E => bus.ppu.bg[3].cnt.raw,
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0x0400_004C => unimplementedRead("Read {} from MOSAIC", .{T}),
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0x0400_004C => readTodo("Read {} from MOSAIC", .{T}),
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// Sound
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0x0400_0060...0x0400_0088 => apu.read(T, &bus.apu, address),
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0x0400_0060...0x0400_009F => apu.read(T, &bus.apu, address),
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// DMA Transfers
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0x0400_00BA...0x0400_00DE => dma.read(T, &bus.dma, address),
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@ -90,20 +92,20 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_0100...0x0400_010E => timer.read(T, &bus.tim, address),
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// Serial Communication 1
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0x0400_0128 => unimplementedRead("Read {} from SIOCNT", .{T}),
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0x0400_0128 => readTodo("Read {} from SIOCNT", .{T}),
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// Keypad Input
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0x0400_0130 => bus.io.keyinput.raw,
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// Serial Communication 2
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0x0400_0134 => unimplementedRead("Read {} from RCNT", .{T}),
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0x0400_0134 => readTodo("Read {} from RCNT", .{T}),
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// Interrupts
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0x0400_0200 => bus.io.ie.raw,
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0x0400_0202 => bus.io.irq.raw,
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0x0400_0204 => unimplementedRead("Read {} from WAITCNT", .{T}),
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0x0400_0204 => readTodo("Read {} from WAITCNT", .{T}),
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0x0400_0208 => @boolToInt(bus.io.ime),
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else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
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},
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u8 => return switch (address) {
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// Display
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@ -120,18 +122,18 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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0x0400_0060...0x0400_0089 => apu.read(T, &bus.apu, address),
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// Serial Communication 1
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0x0400_0128 => unimplementedRead("Read {} from SIOCNT_L", .{T}),
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0x0400_0128 => readTodo("Read {} from SIOCNT_L", .{T}),
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// Keypad Input
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0x0400_0130 => unimplementedRead("read {} from KEYINPUT_L", .{T}),
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0x0400_0130 => readTodo("read {} from KEYINPUT_L", .{T}),
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// Serial Communication 2
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0x0400_0135 => unimplementedRead("Read {} from RCNT_H", .{T}),
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0x0400_0135 => readTodo("Read {} from RCNT_H", .{T}),
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// Interrupts
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0x0400_0200 => @truncate(T, bus.io.ie.raw),
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0x0400_0300 => @enumToInt(bus.io.postflg),
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else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
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},
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else => @compileError("I/O: Unsupported read width"),
|
||||
};
|
||||
|
|
@ -201,7 +203,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
|||
0x0400_0204 => log.debug("Wrote 0x{X:0>8} to WAITCNT", .{value}),
|
||||
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||
0x0400_020C...0x0400_021C => {}, // Unused
|
||||
else => undefinedWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }),
|
||||
else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, address }),
|
||||
},
|
||||
u16 => switch (address) {
|
||||
// Display
|
||||
|
|
@ -283,7 +285,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
|||
0x0400_0204 => log.debug("Wrote 0x{X:0>4} to WAITCNT", .{value}),
|
||||
0x0400_0208 => bus.io.ime = value & 1 == 1,
|
||||
0x0400_0206, 0x0400_020A => {}, // Not Used
|
||||
else => undefinedWrite("Tried to write {} 0x{X:0>4} to 0x{X:0>8}", .{ T, value, address }),
|
||||
else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, address }),
|
||||
},
|
||||
u8 => switch (address) {
|
||||
// Display
|
||||
|
|
@ -315,29 +317,17 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
|
|||
0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
|
||||
|
||||
0x0400_0410 => log.debug("Wrote 0x{X:0>2} to the common yet undocumented 0x{X:0>8}", .{ value, address }),
|
||||
else => undefinedWrite("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
|
||||
else => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, address }),
|
||||
},
|
||||
else => @compileError("I/O: Unsupported write width"),
|
||||
};
|
||||
}
|
||||
|
||||
fn undefinedRead(comptime format: []const u8, args: anytype) u8 {
|
||||
log.debug(format, args);
|
||||
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
fn unimplementedRead(comptime format: []const u8, args: anytype) u8 {
|
||||
fn readTodo(comptime format: []const u8, args: anytype) u8 {
|
||||
log.debug(format, args);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fn undefinedWrite(comptime format: []const u8, args: anytype) void {
|
||||
log.debug(format, args);
|
||||
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
|
||||
}
|
||||
|
||||
/// Read / Write
|
||||
pub const PostFlag = enum(u1) {
|
||||
FirstBoot = 0,
|
||||
|
|
|
|||
|
|
@ -6,6 +6,8 @@ const Scheduler = @import("../scheduler.zig").Scheduler;
|
|||
const Event = @import("../scheduler.zig").Event;
|
||||
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
|
||||
|
||||
const readUndefined = @import("../util.zig").readUndefined;
|
||||
const writeUndefined = @import("../util.zig").writeUndefined;
|
||||
pub const TimerTuple = std.meta.Tuple(&[_]type{ Timer(0), Timer(1), Timer(2), Timer(3) });
|
||||
const log = std.log.scoped(.Timer);
|
||||
|
||||
|
|
@ -22,7 +24,7 @@ pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) T {
|
|||
0x4 => @as(T, tim.*[1].cnt.raw) << 16 | tim.*[1].getCntL(),
|
||||
0x8 => @as(T, tim.*[2].cnt.raw) << 16 | tim.*[2].getCntL(),
|
||||
0xC => @as(T, tim.*[3].cnt.raw) << 16 | tim.*[3].getCntL(),
|
||||
else => @panic("TODO: u32 timer unexpected nybble"),
|
||||
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
|
||||
},
|
||||
u16 => switch (nybble) {
|
||||
0x0 => tim.*[0].getCntL(),
|
||||
|
|
@ -33,10 +35,10 @@ pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) T {
|
|||
0xA => tim.*[2].cnt.raw,
|
||||
0xC => tim.*[3].getCntL(),
|
||||
0xE => tim.*[3].cnt.raw,
|
||||
else => @panic("TODO: u16 timer unexpected nybble"),
|
||||
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
|
||||
},
|
||||
u8 => @panic("TODO: u8 timer unexpected read"),
|
||||
else => @compileError("TIMX: Unsupported read width"),
|
||||
u8 => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
|
||||
else => @compileError("TIM: Unsupported read width"),
|
||||
};
|
||||
}
|
||||
|
||||
|
|
@ -49,7 +51,7 @@ pub fn write(comptime T: type, tim: *TimerTuple, addr: u32, value: T) void {
|
|||
0x4 => tim.*[1].setCnt(value),
|
||||
0x8 => tim.*[2].setCnt(value),
|
||||
0xC => tim.*[3].setCnt(value),
|
||||
else => @panic("TODO: u32 timer unexpected nybble"),
|
||||
else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
|
||||
},
|
||||
u16 => switch (nybble) {
|
||||
0x0 => tim.*[0].setCntL(value),
|
||||
|
|
@ -60,10 +62,10 @@ pub fn write(comptime T: type, tim: *TimerTuple, addr: u32, value: T) void {
|
|||
0xA => tim.*[2].setCntH(value),
|
||||
0xC => tim.*[3].setCntL(value),
|
||||
0xE => tim.*[3].setCntH(value),
|
||||
else => @panic("TODO: u16 timer unexpected nybble"),
|
||||
else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
|
||||
},
|
||||
u8 => @panic("TODO: u8 timer unexpected write"),
|
||||
else => @compileError("TIMX: Unsupported write width"),
|
||||
u8 => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
|
||||
else => @compileError("TIM: Unsupported write width"),
|
||||
};
|
||||
}
|
||||
|
||||
|
|
|
|||
13
src/util.zig
13
src/util.zig
|
|
@ -1,4 +1,5 @@
|
|||
const std = @import("std");
|
||||
const builtin = @import("builtin");
|
||||
const Log2Int = std.math.Log2Int;
|
||||
|
||||
// Sign-Extend value of type `T` to type `U`
|
||||
|
|
@ -99,3 +100,15 @@ pub const FilePaths = struct {
|
|||
bios: ?[]const u8,
|
||||
save: ?[]const u8,
|
||||
};
|
||||
|
||||
pub fn readUndefined(log: anytype, comptime format: []const u8, args: anytype) u8 {
|
||||
log.debug(format, args);
|
||||
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
pub fn writeUndefined(log: anytype, comptime format: []const u8, args: anytype) void {
|
||||
log.debug(format, args);
|
||||
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue