fix(cpu): implement S set + rd == 15 case for data processing
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@ -27,38 +27,32 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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// AND
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const result = op1 & op2;
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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logicFlags(S, cpu, rd, result);
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},
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0x1 => {
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// EOR
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const result = op1 ^ op2;
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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logicFlags(S, cpu, rd, result);
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},
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0x2 => sub(S, cpu, rd, op1, op2), // SUB
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0x3 => sub(S, cpu, rd, op2, op1), // RSB
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0x2 => cpu.r[rd] = sub(S, cpu, rd, op1, op2), // SUB
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0x3 => cpu.r[rd] = sub(S, cpu, rd, op2, op1), // RSB
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0x4 => {
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// ADD
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var result: u32 = undefined;
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const didOverflow = @addWithOverflow(u32, op1, op2, &result);
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(didOverflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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}
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}
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},
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0x5 => {
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// ADC
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@ -68,32 +62,28 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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const overflow = @addWithOverflow(u32, result, old_carry, &result);
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(did or overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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}
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}
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},
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0x6 => sbc(S, cpu, rd, op1, op2, old_carry), // SBC
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0x7 => sbc(S, cpu, rd, op2, op1, old_carry), // RSC
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0x6 => cpu.r[rd] = sbc(S, cpu, rd, op1, op2, old_carry), // SBC
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0x7 => cpu.r[rd] = sbc(S, cpu, rd, op2, op1, old_carry), // RSC
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0x8 => {
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// TST
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const result = op1 & op2;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = shifter.execute(true, cpu, opcode);
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testFlags(S, cpu, opcode, result);
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},
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0x9 => {
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// TEQ
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const result = op1 ^ op2;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TEQ
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if (!S) _ = shifter.execute(true, cpu, opcode);
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testFlags(S, cpu, opcode, result);
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},
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0xA => {
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// CMP
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@ -118,72 +108,81 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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// ORR
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const result = op1 | op2;
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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logicFlags(S, cpu, rd, result);
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},
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0xD => {
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// MOV
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cpu.r[rd] = op2;
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if (S and rd != 0xF) {
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cpu.cpsr.n.write(op2 >> 31 & 1 == 1);
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cpu.cpsr.z.write(op2 == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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logicFlags(S, cpu, rd, op2);
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},
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0xE => {
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// BIC
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const result = op1 & ~op2;
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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logicFlags(S, cpu, rd, result);
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},
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0xF => {
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// MVN
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const result = ~op2;
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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logicFlags(S, cpu, rd, result);
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},
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}
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}
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}.inner;
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}
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fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) void {
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fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
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// TODO: Make your own version (thanks peach.bot)
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const subtrahend = @as(u64, right) - old_carry + 1;
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const result = @truncate(u32, left -% subtrahend);
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(subtrahend <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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}
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return result;
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}
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fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) void {
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fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
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const result = left -% right;
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cpu.r[rd] = result;
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if (S and rd != 0xF) {
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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}
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}
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return result;
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}
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fn logicFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
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if (S) {
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if (rd == 0xF) {
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cpu.setCpsr(cpu.spsr.raw);
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} else {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// C set by Barrel Shifter, V is unaffected
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}
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}
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}
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fn testFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = shifter.execute(true, cpu, opcode);
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}
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