chore: comment ARM MSR code + Audio issues
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@@ -24,12 +24,15 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
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// MSR
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const field_mask = @truncate(u4, opcode >> 16 & 0xF);
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const rm_idx = opcode & 0xF;
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const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx];
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const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) * 2) else cpu.r[rm_idx];
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if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{});
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if (R) {
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if (cpu.isPrivileged()) cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);
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// arm.gba seems to expect the SPSR to do somethign in SYS mode,
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// so we just assume that despite writing to the SPSR in USR or SYS mode
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// being UNPREDICTABLE, it just magically has a working SPSR somehow
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cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);
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} else {
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if (cpu.isPrivileged()) cpu.setCpsr(fieldMask(&cpu.cpsr, field_mask, right));
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}
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@@ -41,6 +44,8 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
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}
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fn fieldMask(psr: *const PSR, field_mask: u4, right: u32) u32 {
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// This bitwise ORs bits 3 and 0 of the field mask into a u2
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// We do this because we only care about bits 7:0 and 31:28 of the CPSR
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const bits = @truncate(u2, (field_mask >> 2 & 0x2) | (field_mask & 1));
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const mask: u32 = switch (bits) {
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