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feat: target Zig v2024.1.0-mach

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This commit is contained in:
Rekai Nyangadzayi Musuka
2024-02-08 23:11:36 -06:00
parent 05b7a9014d
commit 66192daf6c
18 changed files with 129 additions and 80 deletions
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2
src/core/bus/Bios.zig
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@@ -51,7 +51,7 @@ fn _read(self: *const Self, comptime T: type, addr: u32) T {
const buf = self.buf orelse std.debug.panic("[BIOS] ZBA tried to read {} from 0x{X:0>8} but not BIOS was present", .{ T, addr });
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("BIOS: Unsupported read width"),
};
}

4
src/core/bus/Ewram.zig
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@@ -11,7 +11,7 @@ pub fn read(self: *const Self, comptime T: type, address: usize) T {
const addr = address & 0x3FFFF;
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, self.buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("EWRAM: Unsupported read width"),
};
}
@@ -20,7 +20,7 @@ pub fn write(self: *const Self, comptime T: type, address: usize, value: T) void
const addr = address & 0x3FFFF;
return switch (T) {
u32, u16, u8 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u32, u16, u8 => std.mem.writeInt(T, self.buf[addr..][0..@sizeOf(T)], value, .little),
else => @compileError("EWRAM: Unsupported write width"),
};
}

4
src/core/bus/Iwram.zig
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@@ -11,7 +11,7 @@ pub fn read(self: *const Self, comptime T: type, address: usize) T {
const addr = address & 0x7FFF;
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, self.buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("IWRAM: Unsupported read width"),
};
}
@@ -20,7 +20,7 @@ pub fn write(self: *const Self, comptime T: type, address: usize, value: T) void
const addr = address & 0x7FFF;
return switch (T) {
u32, u16, u8 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u32, u16, u8 => std.mem.writeInt(T, self.buf[addr..][0..@sizeOf(T)], value, .little),
else => @compileError("IWRAM: Unsupported write width"),
};
}

6
src/core/bus/backup/eeprom.zig
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@@ -121,7 +121,7 @@ pub const Eeprom = struct {
.Large => {
if (self.writer.len() == 14) {
const addr: u10 = @intCast(self.writer.finish());
const value = std.mem.readIntSliceLittle(u64, buf[@as(u13, addr) * 8 ..][0..8]);
const value = std.mem.readInt(u64, buf[@as(u13, addr) * 8 ..][0..8], .little);
self.reader.configure(value);
self.state = .RequestEnd;
@@ -131,7 +131,7 @@ pub const Eeprom = struct {
if (self.writer.len() == 6) {
// FIXME: Duplicated code from above
const addr: u6 = @intCast(self.writer.finish());
const value = std.mem.readIntSliceLittle(u64, buf[@as(u13, addr) * 8 ..][0..8]);
const value = std.mem.readInt(u64, buf[@as(u13, addr) * 8 ..][0..8], .little);
self.reader.configure(value);
self.state = .RequestEnd;
@@ -159,7 +159,7 @@ pub const Eeprom = struct {
},
.WriteTransfer => {
if (self.writer.len() == 64) {
std.mem.writeIntSliceLittle(u64, buf[self.addr * 8 ..][0..8], self.writer.finish());
std.mem.writeInt(u64, buf[self.addr * 8 ..][0..8], self.writer.finish(), .little);
self.state = .RequestEnd;
}
},

8
src/core/bus/io.zig
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@@ -382,7 +382,7 @@ pub const KeyInput = extern union {
const AtomicKeyInput = struct {
const Self = @This();
const Ordering = std.atomic.Ordering;
const AtomicOrder = std.builtin.AtomicOrder;
inner: KeyInput,
@@ -390,18 +390,18 @@ const AtomicKeyInput = struct {
return .{ .inner = value };
}
pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
pub inline fn load(self: *const Self, comptime ordering: AtomicOrder) u16 {
return switch (ordering) {
.AcqRel, .Release => @compileError("not supported for atomic loads"),
else => @atomicLoad(u16, &self.inner.raw, ordering),
};
}
pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: AtomicOrder) void {
_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
}
pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: AtomicOrder) void {
_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
}
};