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feat: target Zig v2024.1.0-mach

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This commit is contained in:
Rekai Nyangadzayi Musuka
2024-02-08 23:11:36 -06:00
parent 05b7a9014d
commit 66192daf6c
18 changed files with 129 additions and 80 deletions
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4
src/core/apu/signal/Wave.zig
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@@ -18,7 +18,7 @@ pub fn read(self: *const Self, comptime T: type, nr30: io.WaveSelect, addr: u32)
const base = if (!nr30.bank.read()) @as(u32, 0x10) else 0; // Read from the Opposite Bank in Use
const i = base + addr - 0x0400_0090;
return std.mem.readIntSliceLittle(T, self.buf[i..][0..@sizeOf(T)]);
return std.mem.readInt(T, self.buf[i..][0..@sizeOf(T)], .little);
}
pub fn write(self: *Self, comptime T: type, nr30: io.WaveSelect, addr: u32, value: T) void {
@@ -26,7 +26,7 @@ pub fn write(self: *Self, comptime T: type, nr30: io.WaveSelect, addr: u32, valu
const base = if (!nr30.bank.read()) @as(u32, 0x10) else 0; // Write to the Opposite Bank in Use
const i = base + addr - 0x0400_0090;
std.mem.writeIntSliceLittle(T, self.buf[i..][0..@sizeOf(T)], value);
std.mem.writeInt(T, self.buf[i..][0..@sizeOf(T)], value, .little);
}
pub fn init(sched: *Scheduler) Self {

2
src/core/bus/Bios.zig
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@@ -51,7 +51,7 @@ fn _read(self: *const Self, comptime T: type, addr: u32) T {
const buf = self.buf orelse std.debug.panic("[BIOS] ZBA tried to read {} from 0x{X:0>8} but not BIOS was present", .{ T, addr });
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("BIOS: Unsupported read width"),
};
}

4
src/core/bus/Ewram.zig
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@@ -11,7 +11,7 @@ pub fn read(self: *const Self, comptime T: type, address: usize) T {
const addr = address & 0x3FFFF;
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, self.buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("EWRAM: Unsupported read width"),
};
}
@@ -20,7 +20,7 @@ pub fn write(self: *const Self, comptime T: type, address: usize, value: T) void
const addr = address & 0x3FFFF;
return switch (T) {
u32, u16, u8 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u32, u16, u8 => std.mem.writeInt(T, self.buf[addr..][0..@sizeOf(T)], value, .little),
else => @compileError("EWRAM: Unsupported write width"),
};
}

4
src/core/bus/Iwram.zig
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@@ -11,7 +11,7 @@ pub fn read(self: *const Self, comptime T: type, address: usize) T {
const addr = address & 0x7FFF;
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, self.buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("IWRAM: Unsupported read width"),
};
}
@@ -20,7 +20,7 @@ pub fn write(self: *const Self, comptime T: type, address: usize, value: T) void
const addr = address & 0x7FFF;
return switch (T) {
u32, u16, u8 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u32, u16, u8 => std.mem.writeInt(T, self.buf[addr..][0..@sizeOf(T)], value, .little),
else => @compileError("IWRAM: Unsupported write width"),
};
}

6
src/core/bus/backup/eeprom.zig
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@@ -121,7 +121,7 @@ pub const Eeprom = struct {
.Large => {
if (self.writer.len() == 14) {
const addr: u10 = @intCast(self.writer.finish());
const value = std.mem.readIntSliceLittle(u64, buf[@as(u13, addr) * 8 ..][0..8]);
const value = std.mem.readInt(u64, buf[@as(u13, addr) * 8 ..][0..8], .little);
self.reader.configure(value);
self.state = .RequestEnd;
@@ -131,7 +131,7 @@ pub const Eeprom = struct {
if (self.writer.len() == 6) {
// FIXME: Duplicated code from above
const addr: u6 = @intCast(self.writer.finish());
const value = std.mem.readIntSliceLittle(u64, buf[@as(u13, addr) * 8 ..][0..8]);
const value = std.mem.readInt(u64, buf[@as(u13, addr) * 8 ..][0..8], .little);
self.reader.configure(value);
self.state = .RequestEnd;
@@ -159,7 +159,7 @@ pub const Eeprom = struct {
},
.WriteTransfer => {
if (self.writer.len() == 64) {
std.mem.writeIntSliceLittle(u64, buf[self.addr * 8 ..][0..8], self.writer.finish());
std.mem.writeInt(u64, buf[self.addr * 8 ..][0..8], self.writer.finish(), .little);
self.state = .RequestEnd;
}
},

8
src/core/bus/io.zig
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@@ -382,7 +382,7 @@ pub const KeyInput = extern union {
const AtomicKeyInput = struct {
const Self = @This();
const Ordering = std.atomic.Ordering;
const AtomicOrder = std.builtin.AtomicOrder;
inner: KeyInput,
@@ -390,18 +390,18 @@ const AtomicKeyInput = struct {
return .{ .inner = value };
}
pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
pub inline fn load(self: *const Self, comptime ordering: AtomicOrder) u16 {
return switch (ordering) {
.AcqRel, .Release => @compileError("not supported for atomic loads"),
else => @atomicLoad(u16, &self.inner.raw, ordering),
};
}
pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: AtomicOrder) void {
_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
}
pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: AtomicOrder) void {
_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
}
};

45
src/core/emu.zig
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@@ -14,7 +14,7 @@ const isHalted = @import("cpu_util.zig").isHalted;
const Timer = std.time.Timer;
pub const Synchro = struct {
const AtomicBool = std.atomic.Atomic(bool);
const AtomicBool = std.atomic.Value(bool);
// FIXME: This Enum ends up being really LARGE!!!
pub const Message = union(enum) {
@@ -229,6 +229,49 @@ pub const EmuThing = struct {
const Interface = @import("gdbstub").Emulator;
const Allocator = std.mem.Allocator;
pub const target =
\\<target version="1.0">
\\ <architecture>armv4t</architecture>
\\ <feature name="org.gnu.gdb.arm.core">
\\ <reg name="r0" bitsize="32" type="uint32"/>
\\ <reg name="r1" bitsize="32" type="uint32"/>
\\ <reg name="r2" bitsize="32" type="uint32"/>
\\ <reg name="r3" bitsize="32" type="uint32"/>
\\ <reg name="r4" bitsize="32" type="uint32"/>
\\ <reg name="r5" bitsize="32" type="uint32"/>
\\ <reg name="r6" bitsize="32" type="uint32"/>
\\ <reg name="r7" bitsize="32" type="uint32"/>
\\ <reg name="r8" bitsize="32" type="uint32"/>
\\ <reg name="r9" bitsize="32" type="uint32"/>
\\ <reg name="r10" bitsize="32" type="uint32"/>
\\ <reg name="r11" bitsize="32" type="uint32"/>
\\ <reg name="r12" bitsize="32" type="uint32"/>
\\ <reg name="sp" bitsize="32" type="data_ptr"/>
\\ <reg name="lr" bitsize="32"/>
\\ <reg name="pc" bitsize="32" type="code_ptr"/>
\\
\\ <reg name="cpsr" bitsize="32" regnum="25"/>
\\ </feature>
\\</target>
;
// Game Pak SRAM isn't included
// TODO: Can i be more specific here?
pub const map =
\\ <memory-map version="1.0">
\\ <memory type="rom" start="0x00000000" length="0x00004000"/>
\\ <memory type="ram" start="0x02000000" length="0x00040000"/>
\\ <memory type="ram" start="0x03000000" length="0x00008000"/>
\\ <memory type="ram" start="0x04000000" length="0x00000400"/>
\\ <memory type="ram" start="0x05000000" length="0x00000400"/>
\\ <memory type="ram" start="0x06000000" length="0x00018000"/>
\\ <memory type="ram" start="0x07000000" length="0x00000400"/>
\\ <memory type="rom" start="0x08000000" length="0x02000000"/>
\\ <memory type="rom" start="0x0A000000" length="0x02000000"/>
\\ <memory type="rom" start="0x0C000000" length="0x02000000"/>
\\ </memory-map>
;
cpu: *Arm7tdmi,
scheduler: *Scheduler,

4
src/core/ppu/Oam.zig
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@@ -12,7 +12,7 @@ pub fn read(self: *const Self, comptime T: type, address: usize) T {
const addr = address & 0x3FF;
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, self.buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("OAM: Unsupported read width"),
};
}
@@ -21,7 +21,7 @@ pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
const addr = address & 0x3FF;
switch (T) {
u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u32, u16 => std.mem.writeInt(T, self.buf[addr..][0..@sizeOf(T)], value, .little),
u8 => return, // 8-bit writes are explicitly ignored
else => @compileError("OAM: Unsupported write width"),
}

8
src/core/ppu/Palette.zig
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@@ -12,7 +12,7 @@ pub fn read(self: *const Self, comptime T: type, address: usize) T {
const addr = address & 0x3FF;
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, self.buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("PALRAM: Unsupported read width"),
};
}
@@ -21,10 +21,10 @@ pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
const addr = address & 0x3FF;
switch (T) {
u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u32, u16 => std.mem.writeInt(T, self.buf[addr..][0..@sizeOf(T)], value, .little),
u8 => {
const align_addr = addr & ~@as(u32, 1); // Aligned to Halfword boundary
std.mem.writeIntSliceLittle(u16, self.buf[align_addr..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
std.mem.writeInt(u16, self.buf[align_addr..][0..@sizeOf(u16)], @as(u16, value) * 0x101, .little);
},
else => @compileError("PALRAM: Unsupported write width"),
}
@@ -47,5 +47,5 @@ pub fn deinit(self: *Self) void {
}
pub inline fn backdrop(self: *const Self) u16 {
return std.mem.readIntNative(u16, self.buf[0..2]);
return std.mem.readInt(u16, self.buf[0..2], .little);
}

6
src/core/ppu/Vram.zig
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@@ -13,7 +13,7 @@ pub fn read(self: *const Self, comptime T: type, address: usize) T {
const addr = Self.mirror(address);
return switch (T) {
u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
u32, u16, u8 => std.mem.readInt(T, self.buf[addr..][0..@sizeOf(T)], .little),
else => @compileError("VRAM: Unsupported read width"),
};
}
@@ -23,7 +23,7 @@ pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address:
const idx = Self.mirror(address);
switch (T) {
u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[idx..][0..@sizeOf(T)], value),
u32, u16 => std.mem.writeInt(T, self.buf[idx..][0..@sizeOf(T)], value, .little),
u8 => {
// Ignore write if it falls within the boundaries of OBJ VRAM
switch (mode) {
@@ -32,7 +32,7 @@ pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address:
}
const align_idx = idx & ~@as(u32, 1); // Aligned to a halfword boundary
std.mem.writeIntSliceLittle(u16, self.buf[align_idx..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
std.mem.writeInt(u16, self.buf[align_idx..][0..@sizeOf(u16)], @as(u16, value) * 0x101, .little);
},
else => @compileError("VRAM: Unsupported write width"),
}

14
src/main.zig
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@@ -61,7 +61,8 @@ pub fn main() void {
defer allocator.free(config_path);
// Parse CLI
const result = clap.parse(clap.Help, &params, clap.parsers.default, .{}) catch |e| exitln("failed to parse cli: {}", .{e});
const result = clap.parse(clap.Help, &params, clap.parsers.default, .{ .allocator = allocator }) catch |e| exitln("failed to parse cli: {}", .{e});
defer result.deinit();
// TODO: Move config file to XDG Config directory?
@@ -101,8 +102,8 @@ pub fn main() void {
var bus: Bus = undefined;
var ischeduler = IScheduler.init(&scheduler);
var ibus = IBus.init(&bus);
const ischeduler = IScheduler.init(&scheduler);
const ibus = IBus.init(&bus);
var cpu = Arm7tdmi.init(ischeduler, ibus);
@@ -132,7 +133,10 @@ pub fn main() void {
log.info("Ready to connect", .{});
var server = Server.init(emulator) catch |e| exitln("failed to init gdb server: {}", .{e});
var server = Server.init(
emulator,
.{ .memory_map = EmuThing.map, .target = EmuThing.target },
) catch |e| exitln("failed to init gdb server: {}", .{e});
defer server.deinit(allocator);
log.info("Starting GDB Server Thread", .{});
@@ -193,7 +197,7 @@ fn configFilePath(allocator: Allocator, config_path: []const u8) ![]const u8 {
const config_file = std.fs.createFileAbsolute(path, .{}) catch |err| exitln("failed to create \"{s}\": {}", .{ path, err });
defer config_file.close();
try config_file.writeAll(@embedFile("../example.toml"));
try config_file.writeAll(@embedFile("example.toml"));
};
return path;

4
src/util.zig
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@@ -11,13 +11,13 @@ pub const FpsTracker = struct {
const Self = @This();
fps: u32,
count: std.atomic.Atomic(u32),
count: std.atomic.Value(u32),
timer: std.time.Timer,
pub fn init() Self {
return .{
.fps = 0,
.count = std.atomic.Atomic(u32).init(0),
.count = std.atomic.Value(u32).init(0),
.timer = std.time.Timer.start() catch unreachable,
};
}