chore: refactor ARM/THUMB data processing instructions
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@@ -3,12 +3,12 @@ const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const shifter = @import("../barrel_shifter.zig");
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const add = @import("../arm/data_processing.zig").add;
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const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const lsl = @import("../barrel_shifter.zig").logicalLeft;
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const lsr = @import("../barrel_shifter.zig").logicalRight;
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const asr = @import("../barrel_shifter.zig").arithmeticRight;
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pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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return struct {
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@@ -22,7 +22,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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if (offset == 0) {
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break :blk cpu.r[rs];
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} else {
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break :blk shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset);
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break :blk lsl(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b01 => blk: {
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@@ -31,7 +31,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @as(u32, 0);
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} else {
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break :blk shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset);
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break :blk lsr(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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0b10 => blk: {
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@@ -40,7 +40,7 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
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break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
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} else {
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break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset);
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break :blk asr(true, &cpu.cpsr, cpu.r[rs], offset);
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}
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},
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else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
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@@ -48,7 +48,10 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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// Equivalent to an ARM MOVS
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cpu.r[rd] = result;
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setLogicOpFlags(true, cpu, result);
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// Write Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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}
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}.inner;
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}
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@@ -59,35 +62,49 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
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const rd = @as(u4, h1) << 3 | (opcode & 0x7);
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const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
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const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
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const op1 = cpu.r[rd];
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const op2 = cpu.r[rs];
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var result: u32 = undefined;
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var overflow: bool = undefined;
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switch (op) {
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0b00 => {
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// ADD
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const sum = add(false, cpu, rd_value, rs_value);
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cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
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},
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0b01 => cmp(cpu, rd_value, rs_value), // CMP
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0b10 => {
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// MOV
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cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
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},
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0b00 => result = add(&overflow, op1, op2), // ADD
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0b01 => result = op1 -% op2, // CMP
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0b10 => result = op2, // MOV
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0b11 => {},
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}
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// Write to Destination Register
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switch (op) {
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0b01 => {}, // Test Instruction
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0b11 => {
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// BX
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const thumb = rs_value & 1 == 1;
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cpu.r[15] = rs_value & ~@as(u32, 1);
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const is_thumb = op2 & 1 == 1;
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cpu.r[15] = op2 & ~@as(u32, 1);
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cpu.cpsr.t.write(thumb);
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if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
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// TODO: We shouldn't need to worry about the if statement
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// below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
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return;
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cpu.cpsr.t.write(is_thumb);
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if (is_thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
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},
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else => {
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cpu.r[rd] = result;
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if (rd == 0xF) {
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cpu.r[15] &= ~@as(u32, 1);
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cpu.pipe.reload(u16, cpu);
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}
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},
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}
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if (rd == 0xF) cpu.pipe.reload(u16, cpu);
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// Write Flags
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switch (op) {
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0b01 => {
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// CMP
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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},
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0b00, 0b10, 0b11 => {}, // MOV and Branch Instruction
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}
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}
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}.inner;
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}
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@@ -97,21 +114,28 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const rs = opcode >> 3 & 0x7;
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const rd = @truncate(u3, opcode);
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const op1 = cpu.r[rs];
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const op2: u32 = if (I) rn else cpu.r[rn];
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if (is_sub) {
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// SUB
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cpu.r[rd] = if (I) blk: {
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break :blk sub(true, cpu, cpu.r[rs], rn);
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} else blk: {
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break :blk sub(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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const result = op1 -% op2;
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cpu.r[rd] = result;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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} else {
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// ADD
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cpu.r[rd] = if (I) blk: {
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break :blk add(true, cpu, cpu.r[rs], rn);
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} else blk: {
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break :blk add(true, cpu, cpu.r[rs], cpu.r[rn]);
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};
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var overflow: bool = undefined;
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const result = add(&overflow, op1, op2);
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cpu.r[rd] = result;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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}
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}
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}.inner;
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@@ -120,17 +144,36 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
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pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const offset = @truncate(u8, opcode);
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const op1 = cpu.r[rd];
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const op2: u32 = opcode & 0xFF; // Offset
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var overflow: bool = undefined;
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const result: u32 = switch (op) {
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0b00 => op2, // MOV
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0b01 => op1 -% op2, // CMP
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0b10 => add(&overflow, op1, op2), // ADD
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0b11 => op1 -% op2, // SUB
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};
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// Write to Register
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if (op != 0b01) cpu.r[rd] = result;
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// Write Flags
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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switch (op) {
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0b00 => {
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// MOV
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cpu.r[rd] = offset;
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setLogicOpFlags(true, cpu, offset);
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0b00 => {}, // MOV | C set by Barrel Shifter, V is unaffected
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0b01, 0b11 => {
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// SUB, CMP
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cpu.cpsr.c.write(op2 <= op1);
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cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
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},
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0b10 => {
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// ADD
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cpu.cpsr.c.write(overflow);
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cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
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},
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0b01 => cmp(cpu, cpu.r[rd], offset), // CMP
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0b10 => cpu.r[rd] = add(true, cpu, cpu.r[rd], offset), // ADD
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0b11 => cpu.r[rd] = sub(true, cpu, cpu.r[rd], offset), // SUB
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}
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}
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}.inner;
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