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chore: refactor ARM/THUMB data processing instructions

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-09-28 12:46:32 -03:00
parent a3996cbc58
commit 5bb5bdf389
3 changed files with 132 additions and 130 deletions
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57
src/core/cpu/thumb/alu.zig
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@@ -2,7 +2,7 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
const adc = @import("../arm/data_processing.zig").newAdc;
const adc = @import("../arm/data_processing.zig").adc;
const sbc = @import("../arm/data_processing.zig").sbc;
const lsl = @import("../barrel_shifter.zig").logicalLeft;
@@ -17,25 +17,28 @@ pub fn fmt4(comptime op: u4) InstrFn {
const rd = opcode & 0x7;
const carry = @boolToInt(cpu.cpsr.c.read());
const op1 = cpu.r[rd];
const op2 = cpu.r[rs];
var result: u32 = undefined;
var didOverflow: bool = undefined;
var overflow: bool = undefined;
switch (op) {
0x0 => result = cpu.r[rd] & cpu.r[rs], // AND
0x1 => result = cpu.r[rd] ^ cpu.r[rs], // EOR
0x2 => result = lsl(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // LSL
0x3 => result = lsr(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // LSR
0x4 => result = asr(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // ASR
0x5 => result = adc(&didOverflow, cpu.r[rd], cpu.r[rs], carry), // ADC
0x6 => result = sbc(cpu.r[rd], cpu.r[rs], carry), // SBC
0x7 => result = ror(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs])), // ROR
0x8 => result = cpu.r[rd] & cpu.r[rs], // TST
0x9 => result = 0 -% cpu.r[rs], // NEG
0xA => result = cpu.r[rd] -% cpu.r[rs], // CMP
0xB => didOverflow = @addWithOverflow(u32, cpu.r[rd], cpu.r[rs], &result), // CMN
0xC => result = cpu.r[rd] | cpu.r[rs], // ORR
0xD => result = @truncate(u32, @as(u64, cpu.r[rs]) * @as(u64, cpu.r[rd])),
0xE => result = cpu.r[rd] & ~cpu.r[rs],
0xF => result = ~cpu.r[rs],
0x0 => result = op1 & op2, // AND
0x1 => result = op1 ^ op2, // EOR
0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSL
0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSR
0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ASR
0x5 => result = adc(&overflow, op1, op2, carry), // ADC
0x6 => result = sbc(op1, op2, carry), // SBC
0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ROR
0x8 => result = op1 & op2, // TST
0x9 => result = 0 -% op2, // NEG
0xA => result = op1 -% op2, // CMP
0xB => overflow = @addWithOverflow(u32, op1, op2, &result), // CMN
0xC => result = op1 | op2, // ORR
0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
0xE => result = op1 & ~op2,
0xF => result = ~op2,
}
// Write to Destination Register
@@ -60,16 +63,16 @@ pub fn fmt4(comptime op: u4) InstrFn {
if (op == 0xA) {
// CMP specific
cpu.cpsr.c.write(cpu.r[rs] <= cpu.r[rd]);
cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
cpu.cpsr.c.write(op2 <= op1);
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
}
},
0x5, 0xB => {
// ADC, CMN
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (cpu.r[rs] ^ result)) >> 31 & 1 == 1);
cpu.cpsr.c.write(overflow);
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
// FIXME: Pretty sure CMN Is the same
},
@@ -78,16 +81,16 @@ pub fn fmt4(comptime op: u4) InstrFn {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
const subtrahend = @as(u64, cpu.r[rs]) -% carry +% 1;
cpu.cpsr.c.write(subtrahend <= cpu.r[rd]);
cpu.cpsr.v.write(((cpu.r[rd] ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
const subtrahend = @as(u64, op2) -% carry +% 1;
cpu.cpsr.c.write(subtrahend <= op1);
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
},
0x9 => {
// NEG
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(cpu.r[rs] <= 0);
cpu.cpsr.v.write(((0 ^ result) & (~cpu.r[rs] ^ result)) >> 31 & 1 == 1);
cpu.cpsr.c.write(op2 <= 0);
cpu.cpsr.v.write(((0 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
},
0xD => {
// Multiplication