Initial Commit

src/cpu/data_processing.zig

@@ -0,0 +1,56 @@
+const std = @import("std");
+const cpu_mod = @import("../cpu.zig");
+
+const Bus = @import("../bus.zig").Bus;
+const ARM7TDMI = cpu_mod.ARM7TDMI;
+const InstrFn = cpu_mod.InstrFn;
+
+pub fn comptimeDataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+    return struct {
+        fn dataProcessing(cpu: *ARM7TDMI, _: *Bus, opcode: u32) void {
+            const rd = opcode >> 12 & 0xF;
+            const op1 = opcode >> 16 & 0xF;
+
+            var op2: u32 = undefined;
+            if (I) {
+                op2 = std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1);
+            } else {
+                op2 = reg_op2(cpu, opcode);
+            }
+
+            switch (instrKind) {
+                0x4 => {
+                    cpu.r[rd] = cpu.r[op1] + op2;
+
+                    if (S) std.debug.panic("TODO: implement ADD condition codes", .{});
+                },
+                0xD => {
+                    cpu.r[rd] = op2;
+
+                    if (S) std.debug.panic("TODO: implement MOV condition codes", .{});
+                },
+                else => std.debug.panic("TODO: implement data processing type {}", .{instrKind}),
+            }
+        }
+    }.dataProcessing;
+}
+
+fn reg_op2(cpu: *const ARM7TDMI, opcode: u32) u32 {
+    var amount: u32 = undefined;
+    if (opcode >> 4 & 0x01 == 0x01) {
+        amount = cpu.r[opcode >> 8 & 0xF] & 0xFF;
+    } else {
+        amount = opcode >> 7 & 0x1F;
+    }
+
+    const rm = opcode & 0xF;
+    const r_val = cpu.r[rm];
+
+    return switch (opcode >> 5 & 0x03) {
+        0b00 => r_val << @truncate(u5, amount),
+        0b01 => r_val >> @truncate(u5, amount),
+        0b10 => @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount)),
+        0b11 => std.math.rotr(u32, r_val, amount),
+        else => unreachable,
+    };
+}

src/cpu/half_signed_data_transfer.zig

@@ -0,0 +1,67 @@
+const std = @import("std");
+const cpu_mod = @import("../cpu.zig");
+const util = @import("../util.zig");
+
+const Bus = @import("../bus.zig").Bus;
+const ARM7TDMI = cpu_mod.ARM7TDMI;
+const InstrFn = cpu_mod.InstrFn;
+
+pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn halfSignedDataTransfer(cpu: *ARM7TDMI, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+            const rm = opcode & 0xF;
+            const imm_offset_high = opcode >> 8 & 0xF;
+
+            const base = cpu.r[rn];
+
+            var offset: u32 = undefined;
+            if (I) {
+                offset = imm_offset_high << 4 | rm;
+            } else {
+                offset = cpu.r[rm];
+            }
+
+            const modified_base = if (U) base + offset else base - offset;
+            var address = if (P) modified_base else base;
+
+            if (L) {
+                switch(@truncate(u2, opcode >> 5)) {
+                    0b00 => {
+                        // SWP 
+                        std.debug.panic("TODO: Implement SWP", .{});
+                    },
+                    0b01 => {
+                        // LDRH
+                        const halfword = bus.readHalfWord(address);
+                        cpu.r[rd] = @as(u32, halfword);
+                    },
+                    0b10 => {
+                        // LDRSB
+                        const byte = bus.readByte(address);
+                        cpu.r[rd] = util.u32_sign_extend(@as(u32, byte), 8);
+                    },
+                    0b11 => {
+                        // LDRSH
+                        const halfword = bus.readHalfWord(address);
+                        cpu.r[rd] = util.u32_sign_extend(@as(u32, halfword), 16);
+                    }
+                }
+            } else {
+                if (opcode >> 5 & 0x01 == 0x01) {
+                    // STRH
+                    const src = @truncate(u16, cpu.r[rd]);
+
+                    bus.writeHalfWord(address + 2, src);
+                    bus.writeHalfWord(address, src);
+                } else {
+                    std.debug.panic("TODO Figure out if this is also SWP", .{});
+                }
+            }
+
+            address = modified_base;
+            if (W and P) cpu.r[rn] = address;
+        }
+    }.halfSignedDataTransfer;
+}

src/cpu/single_data_transfer.zig

@@ -0,0 +1,64 @@
+const std = @import("std");
+const util = @import("../util.zig");
+const mod_cpu = @import("../cpu.zig");
+
+const ARM7TDMI = mod_cpu.ARM7TDMI;
+const InstrFn = mod_cpu.InstrFn;
+const Bus = @import("../bus.zig").Bus;
+
+pub fn comptimeSingleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn singleDataTransfer(cpu: *ARM7TDMI, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+
+            const base = cpu.r[rn];
+            const offset = if (I) opcode & 0xFFF else registerOffset(cpu, opcode);
+
+            const modified_base = if (U) base + offset else base - offset;
+            var address = if (P) modified_base else base;
+
+            if (L) {
+                if (B) {
+                    // LDRB
+                    cpu.r[rd] = bus.readByte(address);
+                } else {
+                    // LDR
+                    std.debug.panic("Implement LDR", .{});
+                }
+            } else {
+                if (B) {
+                    // STRB
+                    const src = @truncate(u8, cpu.r[rd]);
+
+                    bus.writeByte(address + 3, src);
+                    bus.writeByte(address + 2, src);
+                    bus.writeByte(address + 1, src);
+                    bus.writeByte(address, src);
+                } else {
+                    // STR
+                    std.debug.panic("Implement STR", .{});
+                }
+            }
+
+            address = modified_base;
+            if (W and P) cpu.r[rn] = address;
+
+            // TODO: W-bit forces non-privledged mode for the transfer
+        }
+    }.singleDataTransfer;
+}
+
+fn registerOffset(cpu: *ARM7TDMI, opcode: u32) u32 {
+    const amount = opcode >> 7 & 0x1F;
+    const rm = opcode & 0xF;
+    const r_val = cpu.r[rm];
+
+    return switch (opcode >> 5 & 0x03) {
+        0b00 => r_val << @truncate(u5, amount),
+        0b01 => r_val >> @truncate(u5, amount),
+        0b10 => @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount)),
+        0b11 => std.math.rotr(u32, r_val, amount),
+        else => unreachable,
+    };
+}