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fix: flush pipline on mode change

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-07-02 03:42:27 -03:00
parent 379e667704
commit 5a9c0c2f19
1 changed files with 8 additions and 3 deletions
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11
src/cpu.zig
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@ -156,6 +156,14 @@ pub const Arm7tdmi = struct {
pub fn setCpsr(self: *Self, value: u32) void {
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
const new: PSR = .{ .raw = value };
if (self.cpsr.t.read() != new.t.read()) {
// If THUMB to ARM or ARM to THUMB, flush pipeline
self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
self.pipe.flush();
}
self.cpsr.raw = value;
}
@ -239,9 +247,6 @@ pub const Arm7tdmi = struct {
self.spsr = self.banked_spsr[bankedSpsrIndex(next)];
},
}
self.cpsr.mode.write(@enumToInt(next));
self.pipe.flush();
}
pub fn fastBoot(self: *Self) void {