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feat: implement open bus for unmapped i/o

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-09-12 23:01:41 -03:00
parent 0027d3f8a3
commit 59c9ff910e
7 changed files with 78 additions and 58 deletions
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17
src/core/bus/dma.zig
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@@ -1,11 +1,10 @@
const std = @import("std");
const util = @import("../util.zig");
const DmaControl = @import("io.zig").DmaControl;
const Bus = @import("../Bus.zig");
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
const readUndefined = @import("../util.zig").readUndefined;
const writeUndefined = @import("../util.zig").writeUndefined;
pub const DmaTuple = std.meta.Tuple(&[_]type{ DmaController(0), DmaController(1), DmaController(2), DmaController(3) });
const log = std.log.scoped(.DmaTransfer);
@@ -13,7 +12,7 @@ pub fn create() DmaTuple {
return .{ DmaController(0).init(), DmaController(1).init(), DmaController(2).init(), DmaController(3).init() };
}
pub fn read(comptime T: type, dma: *const DmaTuple, addr: u32) T {
pub fn read(comptime T: type, dma: *const DmaTuple, addr: u32) ?T {
const byte = @truncate(u8, addr);
return switch (T) {
@@ -22,16 +21,16 @@ pub fn read(comptime T: type, dma: *const DmaTuple, addr: u32) T {
0xC4 => @as(T, dma.*[1].cnt.raw) << 16,
0xD0 => @as(T, dma.*[2].cnt.raw) << 16,
0xDC => @as(T, dma.*[3].cnt.raw) << 16,
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
},
u16 => switch (byte) {
0xBA => dma.*[0].cnt.raw,
0xC6 => dma.*[1].cnt.raw,
0xD2 => dma.*[2].cnt.raw,
0xDE => dma.*[3].cnt.raw,
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
},
u8 => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
u8 => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
else => @compileError("DMA: Unsupported read width"),
};
}
@@ -53,7 +52,7 @@ pub fn write(comptime T: type, dma: *DmaTuple, addr: u32, value: T) void {
0xD4 => dma.*[3].setSad(value),
0xD8 => dma.*[3].setDad(value),
0xDC => dma.*[3].setCnt(value),
else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
else => util.io.write.undef(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
},
u16 => switch (byte) {
0xB0 => dma.*[0].setSad(setU32L(dma.*[0].sad, value)),
@@ -83,9 +82,9 @@ pub fn write(comptime T: type, dma: *DmaTuple, addr: u32, value: T) void {
0xDA => dma.*[3].setDad(setU32H(dma.*[3].dad, value)),
0xDC => dma.*[3].setCntL(value),
0xDE => dma.*[3].setCntH(value),
else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
else => util.io.write.undef(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
},
u8 => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
u8 => util.io.write.undef(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
else => @compileError("DMA: Unsupported write width"),
}
}

49
src/core/bus/io.zig
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@@ -1,5 +1,9 @@
const std = @import("std");
const builtin = @import("builtin");
const timer = @import("timer.zig");
const dma = @import("dma.zig");
const apu = @import("../apu.zig");
const util = @import("../util.zig");
const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield;
@@ -7,12 +11,6 @@ const Bus = @import("../Bus.zig");
const DmaController = @import("dma.zig").DmaController;
const Scheduler = @import("../scheduler.zig").Scheduler;
const timer = @import("timer.zig");
const dma = @import("dma.zig");
const apu = @import("../apu.zig");
const readUndefined = @import("../util.zig").readUndefined;
const writeUndefined = @import("../util.zig").writeUndefined;
const log = std.log.scoped(.@"I/O");
pub const Io = struct {
@@ -43,7 +41,7 @@ pub const Io = struct {
}
};
pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
pub fn read(bus: *const Bus, comptime T: type, address: u32) ?T {
return switch (T) {
u32 => switch (address) {
// Display
@@ -58,18 +56,18 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_0100...0x0400_010C => timer.read(T, &bus.tim, address),
// Serial Communication 1
0x0400_0128 => readTodo("Read {} from SIOCNT and SIOMLT_SEND", .{T}),
0x0400_0128 => util.io.read.todo(log, "Read {} from SIOCNT and SIOMLT_SEND", .{T}),
// Keypad Input
0x0400_0130 => readTodo("Read {} from KEYINPUT", .{T}),
0x0400_0130 => util.io.read.todo(log, "Read {} from KEYINPUT", .{T}),
// Serial Communication 2
0x0400_0150 => readTodo("Read {} from JOY_RECV", .{T}),
0x0400_0150 => util.io.read.todo(log, "Read {} from JOY_RECV", .{T}),
// Interrupts
0x0400_0200 => @as(T, bus.io.irq.raw) << 16 | bus.io.ie.raw,
0x0400_0208 => @boolToInt(bus.io.ime),
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
},
u16 => switch (address) {
// Display
@@ -80,7 +78,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_000A => bus.ppu.bg[1].cnt.raw,
0x0400_000C => bus.ppu.bg[2].cnt.raw,
0x0400_000E => bus.ppu.bg[3].cnt.raw,
0x0400_004C => readTodo("Read {} from MOSAIC", .{T}),
0x0400_004C => util.io.read.todo(log, "Read {} from MOSAIC", .{T}),
0x0400_0050 => bus.ppu.bldcnt.raw,
// Sound
@@ -93,20 +91,20 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_0100...0x0400_010E => timer.read(T, &bus.tim, address),
// Serial Communication 1
0x0400_0128 => readTodo("Read {} from SIOCNT", .{T}),
0x0400_0128 => util.io.read.todo(log, "Read {} from SIOCNT", .{T}),
// Keypad Input
0x0400_0130 => bus.io.keyinput.raw,
// Serial Communication 2
0x0400_0134 => readTodo("Read {} from RCNT", .{T}),
0x0400_0134 => util.io.read.todo(log, "Read {} from RCNT", .{T}),
// Interrupts
0x0400_0200 => bus.io.ie.raw,
0x0400_0202 => bus.io.irq.raw,
0x0400_0204 => readTodo("Read {} from WAITCNT", .{T}),
0x0400_0204 => util.io.read.todo(log, "Read {} from WAITCNT", .{T}),
0x0400_0208 => @boolToInt(bus.io.ime),
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
},
u8 => return switch (address) {
// Display
@@ -123,18 +121,18 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_0060...0x0400_00A7 => apu.read(T, &bus.apu, address),
// Serial Communication 1
0x0400_0128 => readTodo("Read {} from SIOCNT_L", .{T}),
0x0400_0128 => util.io.read.todo(log, "Read {} from SIOCNT_L", .{T}),
// Keypad Input
0x0400_0130 => readTodo("read {} from KEYINPUT_L", .{T}),
0x0400_0130 => util.io.read.todo(log, "read {} from KEYINPUT_L", .{T}),
// Serial Communication 2
0x0400_0135 => readTodo("Read {} from RCNT_H", .{T}),
0x0400_0135 => util.io.read.todo(log, "Read {} from RCNT_H", .{T}),
// Interrupts
0x0400_0200 => @truncate(T, bus.io.ie.raw),
0x0400_0300 => @enumToInt(bus.io.postflg),
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, address }),
},
else => @compileError("I/O: Unsupported read width"),
};
@@ -210,7 +208,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0204 => log.debug("Wrote 0x{X:0>8} to WAITCNT", .{value}),
0x0400_0208 => bus.io.ime = value & 1 == 1,
0x0400_020C...0x0400_021C => {}, // Unused
else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, address }),
else => util.io.write.undef(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, address }),
},
u16 => switch (address) {
// Display
@@ -292,7 +290,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0204 => log.debug("Wrote 0x{X:0>4} to WAITCNT", .{value}),
0x0400_0208 => bus.io.ime = value & 1 == 1,
0x0400_0206, 0x0400_020A => {}, // Not Used
else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, address }),
else => util.io.write.undef(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, address }),
},
u8 => switch (address) {
// Display
@@ -325,17 +323,12 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
0x0400_0410 => log.debug("Wrote 0x{X:0>2} to the common yet undocumented 0x{X:0>8}", .{ value, address }),
else => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, address }),
else => util.io.write.undef(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, address }),
},
else => @compileError("I/O: Unsupported write width"),
};
}
fn readTodo(comptime format: []const u8, args: anytype) u8 {
log.debug(format, args);
return 0;
}
/// Read / Write
pub const PostFlag = enum(u1) {
FirstBoot = 0,

17
src/core/bus/timer.zig
View File

@@ -1,4 +1,5 @@
const std = @import("std");
const util = @import("../util.zig");
const TimerControl = @import("io.zig").TimerControl;
const Io = @import("io.zig").Io;
@@ -6,8 +7,6 @@ const Scheduler = @import("../scheduler.zig").Scheduler;
const Event = @import("../scheduler.zig").Event;
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
const readUndefined = @import("../util.zig").readUndefined;
const writeUndefined = @import("../util.zig").writeUndefined;
pub const TimerTuple = std.meta.Tuple(&[_]type{ Timer(0), Timer(1), Timer(2), Timer(3) });
const log = std.log.scoped(.Timer);
@@ -15,7 +14,7 @@ pub fn create(sched: *Scheduler) TimerTuple {
return .{ Timer(0).init(sched), Timer(1).init(sched), Timer(2).init(sched), Timer(3).init(sched) };
}
pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) T {
pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) ?T {
const nybble = @truncate(u4, addr);
return switch (T) {
@@ -24,7 +23,7 @@ pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) T {
0x4 => @as(T, tim.*[1].cnt.raw) << 16 | tim.*[1].getCntL(),
0x8 => @as(T, tim.*[2].cnt.raw) << 16 | tim.*[2].getCntL(),
0xC => @as(T, tim.*[3].cnt.raw) << 16 | tim.*[3].getCntL(),
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
},
u16 => switch (nybble) {
0x0 => tim.*[0].getCntL(),
@@ -35,9 +34,9 @@ pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) T {
0xA => tim.*[2].cnt.raw,
0xC => tim.*[3].getCntL(),
0xE => tim.*[3].cnt.raw,
else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
else => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
},
u8 => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
u8 => util.io.read.undef(T, log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
else => @compileError("TIM: Unsupported read width"),
};
}
@@ -51,7 +50,7 @@ pub fn write(comptime T: type, tim: *TimerTuple, addr: u32, value: T) void {
0x4 => tim.*[1].setCnt(value),
0x8 => tim.*[2].setCnt(value),
0xC => tim.*[3].setCnt(value),
else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
else => util.io.write.undef(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
},
u16 => switch (nybble) {
0x0 => tim.*[0].setCntL(value),
@@ -62,9 +61,9 @@ pub fn write(comptime T: type, tim: *TimerTuple, addr: u32, value: T) void {
0xA => tim.*[2].setCntH(value),
0xC => tim.*[3].setCntL(value),
0xE => tim.*[3].setCntH(value),
else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
else => util.io.write.undef(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
},
u8 => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
u8 => util.io.write.undef(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
else => @compileError("TIM: Unsupported write width"),
};
}