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fix(cpu): implement S set + rd == 15 case for data processing

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-10-21 05:12:01 -03:00
parent eb632056a2
commit 56e660714c
1 changed files with 73 additions and 74 deletions
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115
src/cpu/arm/data_processing.zig
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@ -27,38 +27,32 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
// AND // AND
const result = op1 & op2; const result = op1 & op2;
cpu.r[rd] = result; cpu.r[rd] = result;
logicFlags(S, cpu, rd, result);
if (S and rd != 0xF) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
}
}, },
0x1 => { 0x1 => {
// EOR // EOR
const result = op1 ^ op2; const result = op1 ^ op2;
cpu.r[rd] = result; cpu.r[rd] = result;
logicFlags(S, cpu, rd, result);
if (S and rd != 0xF) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
}
}, },
0x2 => sub(S, cpu, rd, op1, op2), // SUB 0x2 => cpu.r[rd] = sub(S, cpu, rd, op1, op2), // SUB
0x3 => sub(S, cpu, rd, op2, op1), // RSB 0x3 => cpu.r[rd] = sub(S, cpu, rd, op2, op1), // RSB
0x4 => { 0x4 => {
// ADD // ADD
var result: u32 = undefined; var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, op1, op2, &result); const didOverflow = @addWithOverflow(u32, op1, op2, &result);
cpu.r[rd] = result; cpu.r[rd] = result;
if (S and rd != 0xF) { if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0); cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(didOverflow); cpu.cpsr.c.write(didOverflow);
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1); cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
} }
}
}, },
0x5 => { 0x5 => {
// ADC // ADC
@ -68,32 +62,28 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
const overflow = @addWithOverflow(u32, result, old_carry, &result); const overflow = @addWithOverflow(u32, result, old_carry, &result);
cpu.r[rd] = result; cpu.r[rd] = result;
if (S and rd != 0xF) { if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0); cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(did or overflow); cpu.cpsr.c.write(did or overflow);
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1); cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
} }
}
}, },
0x6 => sbc(S, cpu, rd, op1, op2, old_carry), // SBC 0x6 => cpu.r[rd] = sbc(S, cpu, rd, op1, op2, old_carry), // SBC
0x7 => sbc(S, cpu, rd, op2, op1, old_carry), // RSC 0x7 => cpu.r[rd] = sbc(S, cpu, rd, op2, op1, old_carry), // RSC
0x8 => { 0x8 => {
// TST // TST
const result = op1 & op2; const result = op1 & op2;
testFlags(S, cpu, opcode, result);
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// Barrel Shifter should always calc CPSR C in TST
if (!S) _ = shifter.execute(true, cpu, opcode);
}, },
0x9 => { 0x9 => {
// TEQ // TEQ
const result = op1 ^ op2; const result = op1 ^ op2;
testFlags(S, cpu, opcode, result);
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// Barrel Shifter should always calc CPSR C in TEQ
if (!S) _ = shifter.execute(true, cpu, opcode);
}, },
0xA => { 0xA => {
// CMP // CMP
@ -118,72 +108,81 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
// ORR // ORR
const result = op1 | op2; const result = op1 | op2;
cpu.r[rd] = result; cpu.r[rd] = result;
logicFlags(S, cpu, rd, result);
if (S and rd != 0xF) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
}
}, },
0xD => { 0xD => {
// MOV // MOV
cpu.r[rd] = op2; cpu.r[rd] = op2;
logicFlags(S, cpu, rd, op2);
if (S and rd != 0xF) {
cpu.cpsr.n.write(op2 >> 31 & 1 == 1);
cpu.cpsr.z.write(op2 == 0);
// C set by Barrel Shifter, V is unaffected
}
}, },
0xE => { 0xE => {
// BIC // BIC
const result = op1 & ~op2; const result = op1 & ~op2;
cpu.r[rd] = result; cpu.r[rd] = result;
logicFlags(S, cpu, rd, result);
if (S and rd != 0xF) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
}
}, },
0xF => { 0xF => {
// MVN // MVN
const result = ~op2; const result = ~op2;
cpu.r[rd] = result; cpu.r[rd] = result;
logicFlags(S, cpu, rd, result);
if (S and rd != 0xF) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
}
}, },
} }
} }
}.inner; }.inner;
} }
fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) void { fn sbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
// TODO: Make your own version (thanks peach.bot) // TODO: Make your own version (thanks peach.bot)
const subtrahend = @as(u64, right) - old_carry + 1; const subtrahend = @as(u64, right) - old_carry + 1;
const result = @truncate(u32, left -% subtrahend); const result = @truncate(u32, left -% subtrahend);
cpu.r[rd] = result;
if (S and rd != 0xF) { if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0); cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(subtrahend <= left); cpu.cpsr.c.write(subtrahend <= left);
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1); cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
} }
}
return result;
} }
fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) void { fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
const result = left -% right; const result = left -% right;
cpu.r[rd] = result;
if (S and rd != 0xF) { if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0); cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(right <= left); cpu.cpsr.c.write(right <= left);
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1); cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
} }
}
return result;
}
fn logicFlags(comptime S: bool, cpu: *Arm7tdmi, rd: u4, result: u32) void {
if (S) {
if (rd == 0xF) {
cpu.setCpsr(cpu.spsr.raw);
} else {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// C set by Barrel Shifter, V is unaffected
}
}
}
fn testFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) void {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
// Barrel Shifter should always calc CPSR C in TST
if (!S) _ = shifter.execute(true, cpu, opcode);
} }