chore: change directory structure
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201
src/core/bus/timer.zig
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201
src/core/bus/timer.zig
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const std = @import("std");
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const TimerControl = @import("io.zig").TimerControl;
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const Io = @import("io.zig").Io;
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const Scheduler = @import("../scheduler.zig").Scheduler;
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const Event = @import("../scheduler.zig").Event;
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const readUndefined = @import("../util.zig").readUndefined;
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const writeUndefined = @import("../util.zig").writeUndefined;
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pub const TimerTuple = std.meta.Tuple(&[_]type{ Timer(0), Timer(1), Timer(2), Timer(3) });
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const log = std.log.scoped(.Timer);
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pub fn create(sched: *Scheduler) TimerTuple {
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return .{ Timer(0).init(sched), Timer(1).init(sched), Timer(2).init(sched), Timer(3).init(sched) };
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}
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pub fn read(comptime T: type, tim: *const TimerTuple, addr: u32) T {
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const nybble = @truncate(u4, addr);
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return switch (T) {
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u32 => switch (nybble) {
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0x0 => @as(T, tim.*[0].cnt.raw) << 16 | tim.*[0].getCntL(),
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0x4 => @as(T, tim.*[1].cnt.raw) << 16 | tim.*[1].getCntL(),
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0x8 => @as(T, tim.*[2].cnt.raw) << 16 | tim.*[2].getCntL(),
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0xC => @as(T, tim.*[3].cnt.raw) << 16 | tim.*[3].getCntL(),
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u16 => switch (nybble) {
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0x0 => tim.*[0].getCntL(),
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0x2 => tim.*[0].cnt.raw,
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0x4 => tim.*[1].getCntL(),
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0x6 => tim.*[1].cnt.raw,
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0x8 => tim.*[2].getCntL(),
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0xA => tim.*[2].cnt.raw,
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0xC => tim.*[3].getCntL(),
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0xE => tim.*[3].cnt.raw,
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else => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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},
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u8 => readUndefined(log, "Tried to perform a {} read to 0x{X:0>8}", .{ T, addr }),
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else => @compileError("TIM: Unsupported read width"),
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};
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}
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pub fn write(comptime T: type, tim: *TimerTuple, addr: u32, value: T) void {
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const nybble = @truncate(u4, addr);
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return switch (T) {
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u32 => switch (nybble) {
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0x0 => tim.*[0].setCnt(value),
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0x4 => tim.*[1].setCnt(value),
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0x8 => tim.*[2].setCnt(value),
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0xC => tim.*[3].setCnt(value),
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else => writeUndefined(log, "Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u16 => switch (nybble) {
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0x0 => tim.*[0].setCntL(value),
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0x2 => tim.*[0].setCntH(value),
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0x4 => tim.*[1].setCntL(value),
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0x6 => tim.*[1].setCntH(value),
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0x8 => tim.*[2].setCntL(value),
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0xA => tim.*[2].setCntH(value),
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0xC => tim.*[3].setCntL(value),
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0xE => tim.*[3].setCntH(value),
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else => writeUndefined(log, "Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
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},
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u8 => writeUndefined(log, "Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
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else => @compileError("TIM: Unsupported write width"),
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};
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}
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fn Timer(comptime id: u2) type {
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return struct {
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const Self = @This();
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/// Read Only, Internal. Please use self.getCntL()
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_counter: u16,
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/// Write Only, Internal. Please use self.setCntL()
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_reload: u16,
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/// Write Only, Internal. Please use self.setCntH()
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cnt: TimerControl,
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/// Internal.
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sched: *Scheduler,
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/// Internal
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_start_timestamp: u64,
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pub fn init(sched: *Scheduler) Self {
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return .{
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._reload = 0,
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._counter = 0,
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.cnt = .{ .raw = 0x0000 },
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.sched = sched,
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._start_timestamp = 0,
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};
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}
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/// TIMCNT_L
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pub fn getCntL(self: *const Self) u16 {
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if (self.cnt.cascade.read() or !self.cnt.enabled.read()) return self._counter;
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return self._counter +% @truncate(u16, (self.sched.now() - self._start_timestamp) / self.frequency());
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}
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/// TIMCNT_L
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pub fn setCntL(self: *Self, halfword: u16) void {
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self._reload = halfword;
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}
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/// TIMCNT_L & TIMCNT_H
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pub fn setCnt(self: *Self, word: u32) void {
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self.setCntL(@truncate(u16, word));
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self.setCntH(@truncate(u16, word >> 16));
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}
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/// TIMCNT_H
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pub fn setCntH(self: *Self, halfword: u16) void {
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const new = TimerControl{ .raw = halfword };
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// If Timer happens to be enabled, It will either be resheduled or disabled
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self.sched.removeScheduledEvent(.{ .TimerOverflow = id });
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if (self.cnt.enabled.read() and (new.cascade.read() or !new.enabled.read())) {
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// Either through the cascade bit or the enable bit, the timer has effectively been disabled
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// The Counter should hold whatever value it should have been at when it was disabled
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self._counter +%= @truncate(u16, (self.sched.now() - self._start_timestamp) / self.frequency());
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}
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// The counter is only reloaded on the rising edge of the enable bit
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if (!self.cnt.enabled.read() and new.enabled.read()) self._counter = self._reload;
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// If Timer is enabled and we're not cascading, we need to schedule an overflow event
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if (new.enabled.read() and !new.cascade.read()) self.scheduleOverflow(0);
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self.cnt.raw = halfword;
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}
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pub fn handleOverflow(self: *Self, cpu: *Arm7tdmi, late: u64) void {
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// Fire IRQ if enabled
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const io = &cpu.bus.io;
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if (self.cnt.irq.read()) {
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switch (id) {
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0 => io.irq.tim0.set(),
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1 => io.irq.tim1.set(),
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2 => io.irq.tim2.set(),
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3 => io.irq.tim3.set(),
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}
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cpu.handleInterrupt();
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}
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// DMA Sound Things
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if (id == 0 or id == 1) {
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cpu.bus.apu.handleTimerOverflow(cpu, id);
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}
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// Perform Cascade Behaviour
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switch (id) {
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0 => if (cpu.bus.tim[1].cnt.cascade.read()) {
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cpu.bus.tim[1]._counter +%= 1;
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if (cpu.bus.tim[1]._counter == 0) cpu.bus.tim[1].handleOverflow(cpu, late);
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},
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1 => if (cpu.bus.tim[2].cnt.cascade.read()) {
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cpu.bus.tim[2]._counter +%= 1;
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if (cpu.bus.tim[2]._counter == 0) cpu.bus.tim[2].handleOverflow(cpu, late);
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},
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2 => if (cpu.bus.tim[3].cnt.cascade.read()) {
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cpu.bus.tim[3]._counter +%= 1;
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if (cpu.bus.tim[3]._counter == 0) cpu.bus.tim[3].handleOverflow(cpu, late);
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},
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3 => {}, // There is no Timer for TIM3 to "cascade" to,
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}
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// Reschedule Timer if we're not cascading
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if (!self.cnt.cascade.read()) {
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self._counter = self._reload;
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self.scheduleOverflow(late);
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}
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}
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fn scheduleOverflow(self: *Self, late: u64) void {
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const when = (@as(u64, 0x10000) - self._counter) * self.frequency();
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self._start_timestamp = self.sched.now();
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self.sched.push(.{ .TimerOverflow = id }, when -| late);
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}
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fn frequency(self: *const Self) u16 {
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return switch (self.cnt.frequency.read()) {
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0 => 1,
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1 => 64,
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2 => 256,
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3 => 1024,
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};
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}
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};
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}
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