feat(cpu): implement LDM/STM

src/cpu.zig

@@ -10,6 +10,7 @@ const Scheduler = @import("scheduler.zig").Scheduler;
 const dataProcessing = @import("cpu/data_processing.zig").dataProcessing;
 const singleDataTransfer = @import("cpu/single_data_transfer.zig").singleDataTransfer;
 const halfAndSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
+const blockDataTransfer = @import("cpu/block_data_transfer.zig").blockDataTransfer;
 const branch = @import("cpu/branch.zig").branch;
 
 pub const InstrFn = fn (*Arm7tdmi, *Bus, u32) void;
@@ -153,6 +154,16 @@ fn populate() [0x1000]InstrFn {
                 lut[i] = singleDataTransfer(I, P, U, B, W, L);
             }
 
+            if (i >> 9 & 0x7 == 0b100) {
+                const P = i >> 8 & 1 == 1;
+                const U = i >> 7 & 1 == 1;
+                const S = i >> 6 & 1 == 1;
+                const W = i >> 5 & 1 == 1;
+                const L = i >> 4 & 1 == 1;
+
+                lut[i] = blockDataTransfer(P, U, S, W, L);
+            }
+
             if (i >> 9 & 0x7 == 0b101) {
                 const L = i >> 8 & 1 == 1;
                 lut[i] = branch(L);

src/cpu/block_data_transfer.zig

@@ -0,0 +1,55 @@
+const std = @import("std");
+
+const Bus = @import("../Bus.zig");
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../cpu.zig").InstrFn;
+
+pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            var base = cpu.r[rn];
+
+            // TODO: For Performance (?) if U we got from 0 -> 0xF, if !U, 0xF -> 0
+            // we can do this and have it be fast because of comptime, baby!
+
+            if (!U) {
+                var count: u32 = 0;
+                var i: u5 = 0;
+                while (i < 0x10) : (i += 1) {
+                    count += opcode >> i & 1;
+                }
+
+                base -= count * 4;
+            }
+
+            var address = if (@boolToInt(P) ^ @boolToInt(U) == 0) base + 4 else base;
+            if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
+
+            var i: u5 = 0;
+            while (i < 0x10) : (i += 1) {
+                if (opcode >> i & 1 == 1) {
+                    if (L) {
+                        cpu.r[i] = bus.read32(address);
+                        if (S and i == 0xF) std.debug.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
+                    } else {
+                        if (i == 0xF) {
+                            if (!S) {
+                                // TODO: Assure that this is Address of STM instruction + 12
+                                bus.write32(address, cpu.r[i] + (12 - 4));
+                            } else {
+                                std.debug.panic("[CPU] TODO: STM with S set and R15 in transfer list", .{});
+                            }
+                        } else {
+                            bus.write32(address, cpu.r[i]);
+                        }
+                    }
+
+                    address += 4;
+                }
+            }
+
+            if (W and P or !P) cpu.r[rn] = if (U) address - 4 else base;
+        }
+    }.inner;
+}