chore: progress towards working pipeline
focus on THMB branching and a little bit of ARM data processing
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@@ -11,8 +11,7 @@ pub fn branch(comptime L: bool) InstrFn {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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if (L) cpu.r[14] = cpu.r[15] - 4;
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const offset = sext(u32, u24, opcode) << 2;
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cpu.r[15] = cpu.r[15] +% offset;
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cpu.r[15] +%= sext(u32, u24, opcode) << 2;
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cpu.pipe.flush();
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}
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}.inner;
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@@ -21,13 +20,8 @@ pub fn branch(comptime L: bool) InstrFn {
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pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const rn = opcode & 0xF;
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if (cpu.r[rn] & 1 == 1) {
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cpu.r[15] = cpu.r[rn] & ~@as(u32, 1);
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cpu.cpsr.t.set();
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} else {
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cpu.r[15] = cpu.r[rn] & ~@as(u32, 3);
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cpu.cpsr.t.unset();
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}
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const thumb = cpu.r[rn] & 1 == 1;
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cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
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cpu.cpsr.t.write(thumb);
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cpu.pipe.flush();
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}
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@@ -15,8 +15,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
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// If certain conditions are met, PC is 12 ahead instead of 8
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// TODO: What are these conditions? I can't remember
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if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
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const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn];
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const op1 = cpu.r[rn];
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var op2: u32 = undefined;
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if (I) {
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@@ -14,13 +14,8 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
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const rn = opcode >> 16 & 0xF;
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const rd = opcode >> 12 & 0xF;
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var base: u32 = undefined;
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if (rn == 0xF) {
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base = cpu.fakePC();
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if (!L) base += 4; // Offset of 12
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} else {
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base = cpu.r[rn];
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}
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// If L is set, there is an offset of 12 from the instruction to the PC
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const base = cpu.r[rn] + if (!L) 4 else @as(u32, 0);
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const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
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