feat: implement obscure behaviour for ARM data processing instrs

When a test instruction is called when rd == 15, then the CPSR is
reloaded from the SPSR, the pipline is not flushed

src/cpu/arm/data_processing.zig

@@ -282,5 +282,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
     @setCold(true);
-    cpu.setCpsr(cpu.spsr.raw);
+    cpu.setCpsrNoFlush(cpu.spsr.raw);
 }