chore: instantly refill the pipeline on flush

I believe this to be necessary in order to get hardware interrupts
working.

thumb.gba test 108 fails but I'm committing anyways (despite the
regression) because this is kind of rebase/merge hell and I have
something that at least sort of works rn

src/core/cpu/thumb/block_data_transfer.zig

@@ -34,7 +34,7 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
                 if (L) {
                     const value = bus.read(u32, address);
                     cpu.r[15] = value & ~@as(u32, 1);
-                    cpu.pipe.flush();
+                    cpu.pipe.reload(u16, cpu);
                 } else {
                     bus.write(u32, address, cpu.r[14]);
                 }
@@ -55,7 +55,7 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
             if (opcode & 0xFF == 0) {
                 if (L) {
                     cpu.r[15] = bus.read(u32, address);
-                    cpu.pipe.flush();
+                    cpu.pipe.reload(u16, cpu);
                 } else {
                     bus.write(u32, address, cpu.r[15] + 2);
                 }

src/core/cpu/thumb/branch.zig

@@ -15,7 +15,7 @@ pub fn fmt16(comptime cond: u4) InstrFn {
             if (!checkCond(cpu.cpsr, cond)) return;
 
             cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
-            cpu.pipe.flush();
+            cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -25,7 +25,7 @@ pub fn fmt18() InstrFn {
         // B but conditional
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
             cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
-            cpu.pipe.flush();
+            cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -43,7 +43,7 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
                 cpu.r[15] = cpu.r[14] +% (offset << 1);
                 cpu.r[14] = next_opcode | 1;
 
-                cpu.pipe.flush();
+                cpu.pipe.reload(u16, cpu);
             } else {
                 // Instruction 1
                 const lr_offset = sext(u32, u11, offset) << 12;

src/core/cpu/thumb/data_processing.zig

@@ -77,10 +77,18 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
                 },
                 0b11 => {
                     // BX
-                    cpu.cpsr.t.write(src & 1 == 1);
-                    cpu.r[15] = src & 0xFFFF_FFFE;
+                    const thumb = src & 1 == 1;
+                    cpu.r[15] = src & ~@as(u32, 1);
+                    cpu.cpsr.t.write(thumb);
+
+                    if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
+
+                    // Pipeline alrady flushed
+                    return; // FIXME: Is this necessary? (Refactor out?)
                 },
             }
+
+            if (dst_idx == 0xF) cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }

src/core/cpu/thumb/software_interrupt.zig

@@ -17,7 +17,7 @@ pub fn fmt17() InstrFn {
             cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
             cpu.r[15] = 0x0000_0008;
-            cpu.pipe.flush();
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }