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fix: improve perf of instructions w/ rotr

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-03-16 22:28:24 -03:00
parent 1921218c7b
commit 39ab363afa
7 changed files with 33 additions and 13 deletions
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5
src/cpu/arm/half_signed_data_transfer.zig
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@@ -5,6 +5,7 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ArmInstrFn;
const sext = @import("../../util.zig").sext;
const rotr = @import("../../util.zig").rotr;
pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
return struct {
@@ -38,7 +39,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
0b01 => {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
result = std.math.rotr(u32, value, 8 * (address & 1));
result = rotr(u32, value, 8 * (address & 1));
},
0b10 => {
// LDRSB
@@ -52,7 +53,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
break :blk sext(16, bus.read16(address));
};
result = std.math.rotr(u32, value, 8 * (address & 1));
result = rotr(u32, value, 8 * (address & 1));
},
0b00 => unreachable, // SWP
}

4
src/cpu/arm/psr_transfer.zig
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@@ -7,6 +7,8 @@ const PSR = @import("../../cpu.zig").PSR;
const log = std.log.scoped(.PsrTransfer);
const rotr = @import("../../util.zig").rotr;
pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
@@ -22,7 +24,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
// MSR
const field_mask = @truncate(u4, opcode >> 16 & 0xF);
const rm_idx = opcode & 0xF;
const right = if (I) std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx];
const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx];
if (R and !cpu.hasSPSR()) log.warn("Tried to write to SPSR in User/System Mode", .{});

4
src/cpu/arm/single_data_swap.zig
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@@ -4,6 +4,8 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ArmInstrFn;
const rotr = @import("../../util.zig").rotr;
pub fn singleDataSwap(comptime B: bool) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
@@ -20,7 +22,7 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
cpu.r[rd] = value;
} else {
// SWP
const value = std.math.rotr(u32, bus.read32(address & 0xFFFF_FFFC), 8 * (address & 0x3));
const value = rotr(u32, bus.read32(address & 0xFFFF_FFFC), 8 * (address & 0x3));
bus.write32(address & 0xFFFF_FFFC, cpu.r[rm]);
cpu.r[rd] = value;
}

4
src/cpu/arm/single_data_transfer.zig
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@@ -6,6 +6,8 @@ const Bus = @import("../../Bus.zig");
const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
const InstrFn = @import("../../cpu.zig").ArmInstrFn;
const rotr = @import("../../util.zig").rotr;
pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
@@ -33,7 +35,7 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
} else {
// LDR
const value = bus.read32(address & 0xFFFF_FFFC);
result = std.math.rotr(u32, value, 8 * (address & 0x3));
result = rotr(u32, value, 8 * (address & 0x3));
}
} else {
if (B) {