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fix: force align reads/writes in memory bus rather than in CPU

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 15:15:44 -03:00
parent a976a5769e
commit 37a360ec07
7 changed files with 108 additions and 104 deletions
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14
src/cpu/thumb/block_data_transfer.zig
View File

@@ -21,9 +21,9 @@ pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
while (i < 8) : (i += 1) {
if (opcode >> i & 1 == 1) {
if (L) {
cpu.r[i] = bus.read32(address & 0xFFFF_FFFC);
cpu.r[i] = bus.read32(address);
} else {
bus.write32(address & 0xFFFF_FFFC, cpu.r[i]);
bus.write32(address, cpu.r[i]);
}
address += 4;
@@ -32,10 +32,10 @@ pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
if (R) {
if (L) {
const value = bus.read32(address & 0xFFFF_FFFC);
const value = bus.read32(address);
cpu.r[15] = value & 0xFFFF_FFFE;
} else {
bus.write32(address & 0xFFFF_FFFC, cpu.r[14]);
bus.write32(address, cpu.r[14]);
}
address += 4;
}
@@ -52,7 +52,7 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
const end_address = cpu.r[rb] + 4 * countRlist(opcode);
if (opcode & 0xFF == 0) {
if (L) cpu.r[15] = bus.read32(address & 0xFFFF_FFFC) else bus.write32(address & 0xFFFF_FFFC, cpu.r[15] + 4);
if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4);
cpu.r[rb] += 0x40;
return;
}
@@ -63,9 +63,9 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
while (i < 8) : (i += 1) {
if (opcode >> i & 1 == 1) {
if (L) {
cpu.r[i] = bus.read32(address & 0xFFFF_FFFC);
cpu.r[i] = bus.read32(address);
} else {
bus.write32(address & 0xFFFF_FFFC, cpu.r[i]);
bus.write32(address, cpu.r[i]);
}
if (!L and first_write) {

20
src/cpu/thumb/data_transfer.zig
View File

@@ -32,7 +32,7 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
switch (op) {
0b00 => {
// STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
bus.write16(address, @truncate(u16, cpu.r[rd]));
},
0b01 => {
// LDSB
@@ -40,7 +40,7 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
},
0b10 => {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
const value = bus.read16(address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
},
0b11 => {
@@ -59,7 +59,7 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
switch (op) {
0b00 => {
// STR
bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
bus.write32(address, cpu.r[rd]);
},
0b01 => {
// STRB
@@ -67,7 +67,7 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
},
0b10 => {
// LDR
const value = bus.read32(address & 0xFFFF_FFFC);
const value = bus.read32(address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
},
0b11 => {
@@ -94,7 +94,7 @@ pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn
} else {
// LDR
const address = cpu.r[rb] + (@as(u32, offset) << 2);
const value = bus.read32(address & 0xFFFF_FFFC);
const value = bus.read32(address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
}
} else {
@@ -105,7 +105,7 @@ pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn
} else {
// STR
const address = cpu.r[rb] + (@as(u32, offset) << 2);
bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
bus.write32(address, cpu.r[rd]);
}
}
}
@@ -122,11 +122,11 @@ pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
if (L) {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
const value = bus.read16(address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
} else {
// STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
bus.write16(address, @truncate(u16, cpu.r[rd]));
}
}
}.inner;
@@ -140,11 +140,11 @@ pub fn format11(comptime L: bool, comptime rd: u3) InstrFn {
if (L) {
// LDR
const value = bus.read32(address & 0xFFFF_FFFC);
const value = bus.read32(address);
cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
} else {
// STR
bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
bus.write32(address, cpu.r[rd]);
}
}
}.inner;