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fix: force align reads/writes in memory bus rather than in CPU

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 15:15:44 -03:00
parent a976a5769e
commit 37a360ec07
7 changed files with 108 additions and 104 deletions
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4
src/cpu/arm/single_data_transfer.zig
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@@ -34,7 +34,7 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
result = bus.read8(address);
} else {
// LDR
const value = bus.read32(address & 0xFFFF_FFFC);
const value = bus.read32(address);
result = rotr(u32, value, 8 * (address & 0x3));
}
} else {
@@ -45,7 +45,7 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
} else {
// STR
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write32(address & 0xFFFF_FFFC, value);
bus.write32(address, value);
}
}