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fix: force align reads/writes in memory bus rather than in CPU

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 15:15:44 -03:00
parent a976a5769e
commit 37a360ec07
7 changed files with 108 additions and 104 deletions
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4
src/cpu/arm/single_data_swap.zig
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@@ -22,8 +22,8 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
cpu.r[rd] = value;
} else {
// SWP
const value = rotr(u32, bus.read32(address & 0xFFFF_FFFC), 8 * (address & 0x3));
bus.write32(address & 0xFFFF_FFFC, cpu.r[rm]);
const value = rotr(u32, bus.read32(address), 8 * (address & 0x3));
bus.write32(address, cpu.r[rm]);
cpu.r[rd] = value;
}
}