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fix: force align reads/writes in memory bus rather than in CPU

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 15:15:44 -03:00
parent a976a5769e
commit 37a360ec07
7 changed files with 108 additions and 104 deletions
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4
src/cpu/arm/half_signed_data_transfer.zig
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@@ -38,7 +38,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
switch (@truncate(u2, opcode >> 5)) {
0b01 => {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
const value = bus.read16(address);
result = rotr(u32, value, 8 * (address & 1));
},
0b10 => {
@@ -60,7 +60,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
} else {
if (opcode >> 5 & 0x01 == 0x01) {
// STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
bus.write16(address, @truncate(u16, cpu.r[rd]));
} else unreachable; // SWP
}