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fix: force align reads/writes in memory bus rather than in CPU

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This commit is contained in:
Rekai Nyangadzayi Musuka
2022-04-08 15:15:44 -03:00
parent a976a5769e
commit 37a360ec07
7 changed files with 108 additions and 104 deletions
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12
src/cpu/arm/block_data_transfer.zig
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@@ -54,9 +54,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
}
if (L) {
cpu.r[15] = bus.read32(und_addr & 0xFFFF_FFFC);
cpu.r[15] = bus.read32(und_addr);
} else {
bus.write32(und_addr & 0xFFFF_FFFC, cpu.r[15] + 8);
bus.write32(und_addr, cpu.r[15] + 8);
}
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@@ -83,9 +83,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
if (L) {
if (S and !r15_present) {
// Always Transfer User mode Registers
cpu.setUserModeRegister(i, bus.read32(address & 0xFFFF_FFFC));
cpu.setUserModeRegister(i, bus.read32(address));
} else {
const value = bus.read32(address & 0xFFFF_FFFC);
const value = bus.read32(address);
cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
}
@@ -94,9 +94,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
// Always Transfer User mode Registers
// This happens regardless if r15 is in the list
const value = cpu.getUserModeRegister(i);
bus.write32(address & 0xFFFF_FFFC, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
bus.write32(address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
} else {
bus.write32(address & 0xFFFF_FFFC, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
bus.write32(address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
}
}
}

4
src/cpu/arm/half_signed_data_transfer.zig
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@@ -38,7 +38,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
switch (@truncate(u2, opcode >> 5)) {
0b01 => {
// LDRH
const value = bus.read16(address & 0xFFFF_FFFE);
const value = bus.read16(address);
result = rotr(u32, value, 8 * (address & 1));
},
0b10 => {
@@ -60,7 +60,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
} else {
if (opcode >> 5 & 0x01 == 0x01) {
// STRH
bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
bus.write16(address, @truncate(u16, cpu.r[rd]));
} else unreachable; // SWP
}

4
src/cpu/arm/single_data_swap.zig
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@@ -22,8 +22,8 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
cpu.r[rd] = value;
} else {
// SWP
const value = rotr(u32, bus.read32(address & 0xFFFF_FFFC), 8 * (address & 0x3));
bus.write32(address & 0xFFFF_FFFC, cpu.r[rm]);
const value = rotr(u32, bus.read32(address), 8 * (address & 0x3));
bus.write32(address, cpu.r[rm]);
cpu.r[rd] = value;
}
}

4
src/cpu/arm/single_data_transfer.zig
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@@ -34,7 +34,7 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
result = bus.read8(address);
} else {
// LDR
const value = bus.read32(address & 0xFFFF_FFFC);
const value = bus.read32(address);
result = rotr(u32, value, 8 * (address & 0x3));
}
} else {
@@ -45,7 +45,7 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
} else {
// STR
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
bus.write32(address & 0xFFFF_FFFC, value);
bus.write32(address, value);
}
}