chore: add mgba compatible (minus disasm) log function
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29
src/cpu.zig
29
src/cpu.zig
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@ -44,6 +44,8 @@ pub const Arm7tdmi = struct {
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pub inline fn step(self: *@This()) u64 {
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pub inline fn step(self: *@This()) u64 {
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const opcode = self.fetch();
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const opcode = self.fetch();
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self.mgbaLog(opcode);
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if (checkCond(&self.cpsr, opcode)) arm_lut[armIdx(opcode)](self, self.bus, opcode);
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if (checkCond(&self.cpsr, opcode)) arm_lut[armIdx(opcode)](self, self.bus, opcode);
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return 1;
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return 1;
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}
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}
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@ -57,6 +59,33 @@ pub const Arm7tdmi = struct {
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fn fakePC(self: *const @This()) u32 {
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fn fakePC(self: *const @This()) u32 {
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return self.r[15] + 4;
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return self.r[15] + 4;
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}
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}
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fn mgbaLog(self: *const @This(), opcode: u32) void {
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const stderr = std.io.getStdErr().writer();
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std.debug.getStderrMutex().lock();
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defer std.debug.getStderrMutex().unlock();
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const r0 = self.r[0];
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const r1 = self.r[1];
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const r2 = self.r[2];
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const r3 = self.r[3];
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const r4 = self.r[4];
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const r5 = self.r[5];
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const r6 = self.r[6];
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const r7 = self.r[7];
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const r8 = self.r[8];
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const r9 = self.r[9];
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const r10 = self.r[10];
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const r11 = self.r[11];
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const r12 = self.r[12];
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const r13 = self.r[13];
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const r14 = self.r[14];
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const r15 = self.r[15];
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const cpsr = self.cpsr.raw;
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nosuspend stderr.print("{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>8}:\n", .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, cpsr, opcode }) catch return;
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}
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};
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};
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fn armIdx(opcode: u32) u12 {
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fn armIdx(opcode: u32) u12 {
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