feat: reimplement cpu logging
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@@ -6,6 +6,7 @@ const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const FilePaths = @import("util.zig").FilePaths;
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const Logger = @import("util.zig").Logger;
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const File = std.fs.File;
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@@ -225,7 +226,7 @@ pub const thumb = struct {
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}
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};
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const enable_logging = false;
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const cpu_logging = @import("emu.zig").cpu_logging;
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const log = std.log.scoped(.Arm7Tdmi);
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pub const Arm7tdmi = struct {
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@@ -247,9 +248,7 @@ pub const Arm7tdmi = struct {
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banked_spsr: [5]PSR,
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log_file: ?*const File,
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log_buf: [0x100]u8,
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binary_log: bool,
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logger: ?Logger,
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pub fn init(sched: *Scheduler, bus: *Bus) Self {
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return Self{
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@@ -261,15 +260,12 @@ pub const Arm7tdmi = struct {
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.banked_fiq = [_]u32{0x00} ** 10,
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.banked_r = [_]u32{0x00} ** 12,
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.banked_spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
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.log_file = null,
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.log_buf = undefined,
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.binary_log = false,
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.logger = null,
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};
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}
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pub fn useLogger(self: *Self, file: *const File, is_binary: bool) void {
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self.log_file = file;
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self.binary_log = is_binary;
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pub fn attach(self: *Self, log_file: std.fs.File) void {
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self.logger = Logger.init(log_file);
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}
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inline fn bankedIdx(mode: Mode, kind: BankedKind) usize {
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@@ -426,12 +422,12 @@ pub const Arm7tdmi = struct {
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pub fn step(self: *Self) void {
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if (self.cpsr.t.read()) {
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const opcode = self.fetch(u16);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
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thumb.lut[thumbIdx(opcode)](self, self.bus, opcode);
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} else {
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const opcode = self.fetch(u32);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
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if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
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arm.lut[armIdx(opcode)](self, self.bus, opcode);
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@@ -509,14 +505,6 @@ pub const Arm7tdmi = struct {
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return self.r[15] + 4;
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}
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fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
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if (self.binary_log) {
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self.skyLog(file) catch unreachable;
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} else {
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self.mgbaLog(file, opcode) catch unreachable;
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}
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}
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pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
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var i: usize = 0;
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while (i < 16) : (i += 4) {
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@@ -574,25 +562,6 @@ pub const Arm7tdmi = struct {
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};
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}
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fn skyLog(self: *const Self, file: *const File) !void {
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var buf: [18 * @sizeOf(u32)]u8 = undefined;
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// Write Registers
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var i: usize = 0;
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while (i < 0x10) : (i += 1) {
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skyWrite(&buf, i, self.r[i]);
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}
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skyWrite(&buf, 0x10, self.cpsr.raw);
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skyWrite(&buf, 0x11, if (self.hasSPSR()) self.spsr.raw else self.cpsr.raw);
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_ = try file.writeAll(&buf);
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}
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fn skyWrite(buf: []u8, i: usize, num: u32) void {
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const j = @sizeOf(u32) * i;
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std.mem.writeIntSliceNative(u32, buf[j..(j + @sizeOf(u32))], num);
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}
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fn mgbaLog(self: *const Self, file: *const File, opcode: u32) !void {
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const thumb_fmt = "{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>4}:\n";
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const arm_fmt = "{X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} {X:0>8} cpsr: {X:0>8} | {X:0>8}:\n";
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