feat: implement ui for register, interrupt

src/core/bus/io.zig

@@ -346,10 +346,10 @@ const InterruptEnable = extern union {
     vblank: Bit(u16, 0),
     hblank: Bit(u16, 1),
     coincidence: Bit(u16, 2),
-    tm0_overflow: Bit(u16, 3),
-    tm1_overflow: Bit(u16, 4),
-    tm2_overflow: Bit(u16, 5),
-    tm3_overflow: Bit(u16, 6),
+    tim0: Bit(u16, 3),
+    tim1: Bit(u16, 4),
+    tim2: Bit(u16, 5),
+    tim3: Bit(u16, 6),
     serial: Bit(u16, 7),
     dma0: Bit(u16, 8),
     dma1: Bit(u16, 9),

src/core/cpu.zig

@@ -647,7 +647,7 @@ pub const PSR = extern union {
     }
 };
 
-const Mode = enum(u5) {
+pub const Mode = enum(u5) {
     User = 0b10000,
     Fiq = 0b10001,
     Irq = 0b10010,
@@ -656,7 +656,7 @@ const Mode = enum(u5) {
     Undefined = 0b11011,
     System = 0b11111,
 
-    fn toString(self: Mode) []const u8 {
+    pub fn toString(self: Mode) []const u8 {
         return switch (self) {
             .User => "usr",
             .Fiq => "fiq",