feat: pass jsmolka memory.gba
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135987745c
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27ad8772ea
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@ -123,7 +123,7 @@ pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
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// Internal Display Memory
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// Internal Display Memory
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0x05 => self.ppu.palette.write(T, align_addr, value),
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0x05 => self.ppu.palette.write(T, align_addr, value),
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0x06 => self.ppu.vram.write(T, align_addr, value),
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0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, align_addr, value),
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0x07 => self.ppu.oam.write(T, align_addr, value),
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0x07 => self.ppu.oam.write(T, align_addr, value),
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// External Memory (Game Pak)
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// External Memory (Game Pak)
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27
src/ppu.zig
27
src/ppu.zig
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@ -457,7 +457,13 @@ const Palette = struct {
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self.buf[addr + 1] = @truncate(u8, value >> 8);
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self.buf[addr + 1] = @truncate(u8, value >> 8);
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self.buf[addr + 0] = @truncate(u8, value >> 0);
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self.buf[addr + 0] = @truncate(u8, value >> 0);
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},
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},
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u8 => return,
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u8 => {
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const halfword: u16 = @as(u16, value) * 0x0101;
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const real_addr = addr & ~@as(u32, 1); // *was* 8-bit read so address won't be aligned
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self.buf[real_addr + 1] = @truncate(u8, halfword >> 8);
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self.buf[real_addr + 0] = @truncate(u8, halfword >> 0);
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},
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else => @compileError("PALRAM: Unsupported write width"),
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else => @compileError("PALRAM: Unsupported write width"),
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}
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}
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}
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}
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@ -498,7 +504,8 @@ const Vram = struct {
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};
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};
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}
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}
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pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
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pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address: usize, value: T) void {
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const mode: u3 = dispcnt.bg_mode.read();
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const addr = Self.mirror(address);
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const addr = Self.mirror(address);
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switch (T) {
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switch (T) {
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@ -512,7 +519,19 @@ const Vram = struct {
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self.buf[addr + 1] = @truncate(u8, value >> 8);
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self.buf[addr + 1] = @truncate(u8, value >> 8);
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self.buf[addr + 0] = @truncate(u8, value >> 0);
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self.buf[addr + 0] = @truncate(u8, value >> 0);
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},
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},
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u8 => return,
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u8 => {
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// Ignore if write is in OBJ
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switch (mode) {
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0, 1, 2 => if (0x0601_0000 <= address and address < 0x0601_8000) return,
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else => if (0x0601_4000 <= address and address < 0x0601_8000) return,
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}
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const halfword: u16 = @as(u16, value) * 0x0101;
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const real_addr = addr & ~@as(u32, 1);
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self.buf[real_addr + 1] = @truncate(u8, halfword >> 8);
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self.buf[real_addr + 0] = @truncate(u8, halfword >> 0);
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},
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else => @compileError("VRAM: Unsupported write width"),
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else => @compileError("VRAM: Unsupported write width"),
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}
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}
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}
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}
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@ -568,7 +587,7 @@ const Oam = struct {
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self.buf[addr + 1] = @truncate(u8, value >> 8);
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self.buf[addr + 1] = @truncate(u8, value >> 8);
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self.buf[addr + 0] = @truncate(u8, value >> 0);
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self.buf[addr + 0] = @truncate(u8, value >> 0);
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},
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},
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u8 => return,
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u8 => return, // 8-bit writes are explicitly ignored
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else => @compileError("OAM: Unsupported write width"),
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else => @compileError("OAM: Unsupported write width"),
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}
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}
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}
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}
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