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feat(cpu): implement RSB

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-01-18 14:36:03 -04:00
parent 63a57ac954
commit 212bc9e11d
1 changed files with 25 additions and 23 deletions
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48
src/cpu/arm/data_processing.zig
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@ -8,7 +8,7 @@ const InstrFn = @import("../../cpu.zig").ArmInstrFn;
pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn { pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
const rd = opcode >> 12 & 0xF; const rd = @truncate(u4, opcode >> 12 & 0xF);
const rn = opcode >> 16 & 0xF; const rn = opcode >> 16 & 0xF;
const old_carry = @boolToInt(cpu.cpsr.c.read()); const old_carry = @boolToInt(cpu.cpsr.c.read());
@ -44,18 +44,8 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
// C set by Barrel Shifter, V is unaffected // C set by Barrel Shifter, V is unaffected
} }
}, },
0x2 => { 0x2 => sub(S, cpu, rd, op1, op2), // SUB
// SUB 0x3 => sub(S, cpu, rd, op2, op1), // RSB
const result = op1 -% op2;
cpu.r[rd] = result;
if (S and rd != 0xF) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(op2 <= op1);
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
}
},
0x4 => { 0x4 => {
// ADD // ADD
var result: u32 = undefined; var result: u32 = undefined;
@ -116,16 +106,6 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
// Barrel Shifter should always calc CPSR C in TEQ // Barrel Shifter should always calc CPSR C in TEQ
if (!S) _ = shifter.execute(true, cpu, opcode); if (!S) _ = shifter.execute(true, cpu, opcode);
}, },
0xD => {
// MOV
cpu.r[rd] = op2;
if (S and rd != 0xF) {
cpu.cpsr.n.write(op2 >> 31 & 1 == 1);
cpu.cpsr.z.write(op2 == 0);
// C set by Barrel Shifter, V is unaffected
}
},
0xA => { 0xA => {
// CMP // CMP
const result = op1 -% op2; const result = op1 -% op2;
@ -146,6 +126,16 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
// C set by Barrel Shifter, V is unaffected // C set by Barrel Shifter, V is unaffected
} }
}, },
0xD => {
// MOV
cpu.r[rd] = op2;
if (S and rd != 0xF) {
cpu.cpsr.n.write(op2 >> 31 & 1 == 1);
cpu.cpsr.z.write(op2 == 0);
// C set by Barrel Shifter, V is unaffected
}
},
0xE => { 0xE => {
// BIC // BIC
const result = op1 & ~op2; const result = op1 & ~op2;
@ -173,3 +163,15 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
} }
}.inner; }.inner;
} }
fn sub(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) void {
const result = left -% right;
cpu.r[rd] = result;
if (S and rd != 0xF) {
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(right <= left);
cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
}
}