chore: reimplement ARM LDM/STM
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@ -7,47 +7,71 @@ const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
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const r15_present = opcode >> 15 & 1 == 1;
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const rn = opcode >> 16 & 0xF;
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var address: u32 = cpu.r[rn];
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const rn = @truncate(u4, opcode >> 16 & 0xF);
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const rlist = opcode & 0xFFFF;
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const r15 = rlist >> 15 & 1 == 1;
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if (opcode & 0xFFFF == 0) {
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if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 8);
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cpu.r[rn] += 0x40;
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var count: u32 = 0;
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var i: u5 = 0;
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var first: u4 = 0;
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var write_to_base = true;
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while (i < 16) : (i += 1) {
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const r = @truncate(u4, 15 - i);
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if (rlist >> r & 1 == 1) {
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first = r;
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count += 1;
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}
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}
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var start = cpu.r[rn];
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if (U) {
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start += if (P) 4 else 0;
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} else {
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start = start - (4 * count) + if (!P) 4 else 0;
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}
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var end = cpu.r[rn];
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if (U) {
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end = end + (4 * count) - if (!P) 4 else 0;
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} else {
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end -= if (P) 4 else 0;
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}
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var new_base = cpu.r[rn];
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if (U) {
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new_base += 4 * count;
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} else {
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new_base -= 4 * count;
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}
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var address = start;
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if (rlist == 0) {
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if (L) {
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cpu.r[15] = bus.read32(address);
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} else {
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bus.write32(address, cpu.r[15] + 8);
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}
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cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
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return;
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}
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if (U) {
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// Increment
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var i: u5 = 0;
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while (i < 0x10) : (i += 1) {
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if (opcode >> i & 1 == 1) {
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if (P) address += 4;
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transfer(cpu, bus, r15_present, i, address);
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if (!P) address += 4;
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}
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}
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} else {
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// Decrement
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i = first;
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while (i < 16) : (i += 1) {
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if (rlist >> i & 1 == 1) {
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transfer(cpu, bus, r15, i, address);
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address += 4;
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var i: u5 = 0x10;
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while (i > 0) : (i -= 1) {
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const j = i - 1;
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if (opcode >> j & 1 == 1) {
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if (P) address -= 4;
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transfer(cpu, bus, r15_present, j, address);
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if (!P) address -= 4;
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if (W and !L and write_to_base) {
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cpu.r[rn] = new_base;
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write_to_base = false;
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}
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}
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}
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if (W) {
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const in_list = opcode >> @truncate(u4, rn) & 1 == 1;
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if (!L or (L and !in_list)) {
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cpu.r[rn] = address;
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}
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}
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if (W and L and opcode >> rn & 1 == 0) cpu.r[rn] = new_base;
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}
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fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void {
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