paoda/zba
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

chore: reimplement ARM LDM/STM

Browse Source
This commit is contained in:
Rekai Nyangadzayi Musuka
2022-10-21 05:12:17 -03:00
parent 130310e5cc
commit 1ee8b51b2b
1 changed files with 56 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
src/cpu/arm/block_data_transfer.zig
View File

@@ -7,47 +7,71 @@ const InstrFn = @import("../../cpu.zig").ArmInstrFn;
pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn { pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
return struct { return struct {
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void { fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
const r15_present = opcode >> 15 & 1 == 1; const rn = @truncate(u4, opcode >> 16 & 0xF);
const rn = opcode >> 16 & 0xF; const rlist = opcode & 0xFFFF;
var address: u32 = cpu.r[rn]; const r15 = rlist >> 15 & 1 == 1;
if (opcode & 0xFFFF == 0) { var count: u32 = 0;
if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 8); var i: u5 = 0;
cpu.r[rn] += 0x40; var first: u4 = 0;
var write_to_base = true;
while (i < 16) : (i += 1) {
const r = @truncate(u4, 15 - i);
if (rlist >> r & 1 == 1) {
first = r;
count += 1;
}
}
var start = cpu.r[rn];
if (U) {
start += if (P) 4 else 0;
} else {
start = start - (4 * count) + if (!P) 4 else 0;
}
var end = cpu.r[rn];
if (U) {
end = end + (4 * count) - if (!P) 4 else 0;
} else {
end -= if (P) 4 else 0;
}
var new_base = cpu.r[rn];
if (U) {
new_base += 4 * count;
} else {
new_base -= 4 * count;
}
var address = start;
if (rlist == 0) {
if (L) {
cpu.r[15] = bus.read32(address);
} else {
bus.write32(address, cpu.r[15] + 8);
}
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
return; return;
} }
if (U) { i = first;
// Increment while (i < 16) : (i += 1) {
var i: u5 = 0; if (rlist >> i & 1 == 1) {
while (i < 0x10) : (i += 1) { transfer(cpu, bus, r15, i, address);
if (opcode >> i & 1 == 1) { address += 4;
if (P) address += 4;
transfer(cpu, bus, r15_present, i, address);
if (!P) address += 4;
}
}
} else {
// Decrement
var i: u5 = 0x10; if (W and !L and write_to_base) {
while (i > 0) : (i -= 1) { cpu.r[rn] = new_base;
const j = i - 1; write_to_base = false;
if (opcode >> j & 1 == 1) {
if (P) address -= 4;
transfer(cpu, bus, r15_present, j, address);
if (!P) address -= 4;
} }
} }
} }
if (W) { if (W and L and opcode >> rn & 1 == 0) cpu.r[rn] = new_base;
const in_list = opcode >> @truncate(u4, rn) & 1 == 1;
if (!L or (L and !in_list)) {
cpu.r[rn] = address;
}
}
} }
fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void { fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void {