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feat: working pipeline implementation

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-09-28 16:11:25 -03:00
parent f466ae2ae2
commit 14ba0dbca9
10 changed files with 31 additions and 45 deletions
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39
src/core/cpu.zig
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@ -324,21 +324,8 @@ pub const Arm7tdmi = struct {
return self.bus.io.haltcnt == .Halt;
}
pub fn setCpsrNoFlush(self: *Self, value: u32) void {
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
self.cpsr.raw = value;
}
pub fn setCpsr(self: *Self, value: u32) void {
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
const new: PSR = .{ .raw = value };
if (self.cpsr.t.read() != new.t.read()) {
// If THUMB to ARM or ARM to THUMB, flush pipeline
self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
if (new.t.read()) self.pipe.reload(u16, self) else self.pipe.reload(u32, self);
}
self.cpsr.raw = value;
}
@ -501,7 +488,8 @@ pub const Arm7tdmi = struct {
// log.debug("Handling Interrupt!", .{});
self.bus.io.haltcnt = .Execute;
const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
// FIXME: This seems weird, but retAddr.gba suggests I need to make these changes
const ret_addr = self.r[15] - if (self.cpsr.t.read()) 0 else @as(u32, 4);
const new_spsr = self.cpsr.raw;
self.changeMode(.Irq);
@ -511,7 +499,7 @@ pub const Arm7tdmi = struct {
self.r[14] = ret_addr;
self.spsr.raw = new_spsr;
self.r[15] = 0x0000_0018;
self.pipe.reload(u32, self);
self.pipe.reload(self);
}
inline fn fetch(self: *Self, comptime T: type) T {
@ -693,18 +681,17 @@ const Pipline = struct {
return opcode;
}
pub fn reload(self: *Self, comptime T: type, cpu: *Arm7tdmi) void {
comptime std.debug.assert(T == u32 or T == u16);
pub fn reload(self: *Self, cpu: *Arm7tdmi) void {
if (cpu.cpsr.t.read()) {
self.stage[0] = cpu.bus.read(u16, cpu.r[15]);
self.stage[1] = cpu.bus.read(u16, cpu.r[15] + 2);
cpu.r[15] += 4;
} else {
self.stage[0] = cpu.bus.read(u32, cpu.r[15]);
self.stage[1] = cpu.bus.read(u32, cpu.r[15] + 4);
cpu.r[15] += 8;
}
// Sometimes, the pipeline can be reloaded twice in the same instruction
// This can happen if:
// 1. R15 is written to
// 2. The CPSR is written to (and T changes), so R15 is written to again
self.stage[0] = cpu.bus.read(T, cpu.r[15]);
self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
self.flushed = true;
}
};

4
src/core/cpu/arm/block_data_transfer.zig
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@ -55,7 +55,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
if (L) {
cpu.r[15] = bus.read(u32, und_addr);
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
} else {
// FIXME: Should r15 on write be +12 ahead?
bus.write(u32, und_addr, cpu.r[15] + 4);
@ -92,7 +92,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
cpu.r[i] = value;
if (i == 0xF) {
cpu.r[i] &= ~@as(u32, 3); // Align r15
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
if (S) cpu.setCpsr(cpu.spsr.raw);
}

4
src/core/cpu/arm/branch.zig
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@ -12,7 +12,7 @@ pub fn branch(comptime L: bool) InstrFn {
if (L) cpu.r[14] = cpu.r[15] - 4;
cpu.r[15] +%= sext(u32, u24, opcode) << 2;
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
}
}.inner;
}
@ -24,5 +24,5 @@ pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
cpu.cpsr.t.write(thumb);
if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
}

7
src/core/cpu/arm/data_processing.zig
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@ -76,9 +76,8 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
else => {
cpu.r[rd] = result;
if (rd == 0xF) {
if (S) cpu.setCpsrNoFlush(cpu.spsr.raw);
cpu.pipe.reload(u32, cpu);
if (S) cpu.setCpsr(cpu.spsr.raw);
cpu.pipe.reload(cpu);
}
},
}
@ -180,5 +179,5 @@ pub fn adc(overflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
@setCold(true);
cpu.setCpsrNoFlush(cpu.spsr.raw);
cpu.setCpsr(cpu.spsr.raw);
}

4
src/core/cpu/arm/single_data_transfer.zig
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@ -47,13 +47,13 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
address = modified_base;
if (W and P or !P) {
cpu.r[rn] = address;
if (rn == 0xF) cpu.pipe.reload(u32, cpu);
if (rn == 0xF) cpu.pipe.reload(cpu);
}
if (L) {
// This emulates the LDR rd == rn behaviour
cpu.r[rd] = result;
if (rd == 0xF) cpu.pipe.reload(u32, cpu);
if (rd == 0xF) cpu.pipe.reload(cpu);
}
}
}.inner;

2
src/core/cpu/arm/software_interrupt.zig
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@ -17,7 +17,7 @@ pub fn armSoftwareInterrupt() InstrFn {
cpu.r[14] = ret_addr; // Resume Execution
cpu.spsr.raw = cpsr; // Previous mode CPSR
cpu.r[15] = 0x0000_0008;
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
}
}.inner;
}

4
src/core/cpu/thumb/block_data_transfer.zig
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@ -34,7 +34,7 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
if (L) {
const value = bus.read(u32, address);
cpu.r[15] = value & ~@as(u32, 1);
cpu.pipe.reload(u16, cpu);
cpu.pipe.reload(cpu);
} else {
bus.write(u32, address, cpu.r[14]);
}
@ -55,7 +55,7 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
if (opcode & 0xFF == 0) {
if (L) {
cpu.r[15] = bus.read(u32, address);
cpu.pipe.reload(u16, cpu);
cpu.pipe.reload(cpu);
} else {
bus.write(u32, address, cpu.r[15] + 2);
}

6
src/core/cpu/thumb/branch.zig
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@ -15,7 +15,7 @@ pub fn fmt16(comptime cond: u4) InstrFn {
if (!checkCond(cpu.cpsr, cond)) return;
cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
cpu.pipe.reload(u16, cpu);
cpu.pipe.reload(cpu);
}
}.inner;
}
@ -25,7 +25,7 @@ pub fn fmt18() InstrFn {
// B but conditional
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
cpu.pipe.reload(u16, cpu);
cpu.pipe.reload(cpu);
}
}.inner;
}
@ -43,7 +43,7 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
cpu.r[15] = cpu.r[14] +% (offset << 1);
cpu.r[14] = next_opcode | 1;
cpu.pipe.reload(u16, cpu);
cpu.pipe.reload(cpu);
} else {
// Instruction 1
const lr_offset = sext(u32, u11, offset) << 12;

4
src/core/cpu/thumb/data_processing.zig
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@ -83,13 +83,13 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
cpu.r[15] = op2 & ~@as(u32, 1);
cpu.cpsr.t.write(is_thumb);
if (is_thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
},
else => {
cpu.r[rd] = result;
if (rd == 0xF) {
cpu.r[15] &= ~@as(u32, 1);
cpu.pipe.reload(u16, cpu);
cpu.pipe.reload(cpu);
}
},
}

2
src/core/cpu/thumb/software_interrupt.zig
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@ -17,7 +17,7 @@ pub fn fmt17() InstrFn {
cpu.r[14] = ret_addr; // Resume Execution
cpu.spsr.raw = cpsr; // Previous mode CPSR
cpu.r[15] = 0x0000_0008;
cpu.pipe.reload(u32, cpu);
cpu.pipe.reload(cpu);
}
}.inner;
}