chore(cpu): lay groundwork for THUMB instruction decoding and execution
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83a5370196
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0eba3aca1f
60
src/cpu.zig
60
src/cpu.zig
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@ -15,8 +15,10 @@ const blockDataTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTr
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const branch = @import("cpu/arm/branch.zig").branch;
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const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
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pub const InstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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const arm_lut: [0x1000]InstrFn = populate();
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pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
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const arm_lut: [0x1000]ArmInstrFn = armPopulate();
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const thumb_lut: [0x400]ThumbInstrFn = thumbPopulate();
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pub const Arm7tdmi = struct {
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const Self = @This();
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@ -49,16 +51,29 @@ pub const Arm7tdmi = struct {
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}
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pub fn step(self: *Self) u64 {
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const opcode = self.fetch();
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// self.mgbaLog(opcode);
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if (self.cpsr.t.read()) {
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const opcode = self.thumbFetch();
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thumb_lut[thumbIdx(opcode)](self, self.bus, opcode);
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} else {
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const opcode = self.fetch();
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if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
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arm_lut[armIdx(opcode)](self, self.bus, opcode);
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}
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}
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if (checkCond(&self.cpsr, opcode)) arm_lut[armIdx(opcode)](self, self.bus, opcode);
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return 1;
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}
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fn thumbFetch(self: *Self) u16 {
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const halfword = self.bus.read16(self.r[15]);
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self.r[15] += 2;
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return halfword;
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}
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fn fetch(self: *Self) u32 {
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const word = self.bus.read32(self.r[15]);
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self.r[15] += if (self.cpsr.t.read()) @as(u32, 2) else @as(u32, 4);
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self.r[15] += 4;
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return word;
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}
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@ -98,9 +113,13 @@ fn armIdx(opcode: u32) u12 {
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return @truncate(u12, opcode >> 20 & 0xFF) << 4 | @truncate(u12, opcode >> 4 & 0xF);
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}
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fn checkCond(cpsr: *const PSR, opcode: u32) bool {
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fn thumbIdx(opcode: u16) u10 {
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return @truncate(u10, opcode >> 6);
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}
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fn checkCond(cpsr: PSR, cond: u4) bool {
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// TODO: Should I implement an enum?
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return switch (@truncate(u4, opcode >> 28)) {
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return switch (cond) {
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0x0 => cpsr.z.read(), // EQ - Equal
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0x1 => !cpsr.z.read(), // NE - Not equal
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0x2 => cpsr.c.read(), // CS - Unsigned higher or same
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@ -120,10 +139,24 @@ fn checkCond(cpsr: *const PSR, opcode: u32) bool {
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};
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}
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fn populate() [0x1000]InstrFn {
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fn thumbPopulate() [0x400]ThumbInstrFn {
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return comptime {
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@setEvalBranchQuota(0x800);
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var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
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var i: usize = 0;
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while (i < lut.len) : (i += 1) {
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lut[i] = thumbUndefined;
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}
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return lut;
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};
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}
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fn armPopulate() [0x1000]ArmInstrFn {
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return comptime {
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@setEvalBranchQuota(0x5000); // TODO: Figure out exact size
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var lut = [_]InstrFn{undefinedInstruction} ** 0x1000;
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var lut = [_]ArmInstrFn{armUndefined} ** 0x1000;
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var i: usize = 0;
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while (i < lut.len) : (i += 1) {
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@ -210,7 +243,12 @@ const Mode = enum(u5) {
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System = 0b11111,
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};
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fn undefinedInstruction(_: *Arm7tdmi, _: *Bus, opcode: u32) void {
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fn armUndefined(_: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const id = armIdx(opcode);
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std.debug.panic("[CPU] {{0x{X:}}} 0x{X:} is an illegal opcode", .{ id, opcode });
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}
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fn thumbUndefined(_: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const id = thumbIdx(opcode);
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std.debug.panic("[CPU] {{0x{X:}}} 0x{X:} is an illegal opcode", .{ id, opcode });
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}
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@ -2,7 +2,7 @@ const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").InstrFn;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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@ -3,7 +3,7 @@ const util = @import("../../util.zig");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").InstrFn;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn branch(comptime L: bool) InstrFn {
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return struct {
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@ -3,7 +3,7 @@ const std = @import("std");
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const BarrelShifter = @import("barrel_shifter.zig");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").InstrFn;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
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return struct {
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@ -3,7 +3,7 @@ const util = @import("../../util.zig");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").InstrFn;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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@ -2,7 +2,7 @@ const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").InstrFn;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn psrTransfer(comptime I: bool, comptime isSpsr: bool) InstrFn {
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return struct {
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@ -5,7 +5,7 @@ const BarrelShifter = @import("barrel_shifter.zig");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const CPSR = @import("../../cpu.zig").PSR;
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const InstrFn = @import("../../cpu.zig").InstrFn;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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